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ADAU1772 Output ASRC Source Select

SigmaDSP & SigmaStudio bklein Mar 13, 2023 00:00 5 replies Original on forum ↗
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bklein Question
Mar 13, 2023 00:00

Please explain the Output ASRC Source Select. I have been using the Core Out X selections but wonder about ADC X selections. They do not seem to have the same levels as the Core outputs. Are they basically using the inputs to the DSP core rather than the outputs? Why not the same level if no level changes are made in the DSP core (straight through no "effects")? Once this resolved should it show a better S/N result if testing ADC > serial out?

software

adau1772

Integrated/Special Purpose A/D Converters

Audio CODECs

DaveThib Reply
Mar 13, 2023 00:00

Hello bklein,

I do not have a great answer for you. There were some gain errors in the design through the system. I have never received a good explanation from the designers. It is written up in the datasheet but it still says "approximately" and I think this diagram is still not correct. You will see about 2.5dB differences in places so it is not anything you are doing wrong.

This section of the datasheet makes an attempt to show the level differences but it does not seem to be fully correct.

You are correct that the level out of the core should be at the same level as coming directly from the ADCs. This diagram in SigmaStudio shows it well.

There is a possibility that you could have a clocking problem. Can you attach your project and let me know what frequency the master clock is running at? Let me know the levels you are seeing and I can verify I have the same measurements here.

Thanks,

Dave T

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bklein Reply
Mar 14, 2023 00:00

RMS level of ADC output is -68dB FS or so down , while using Core output is normal.

MCLK is standard off the eval board and internal (12.288MHz)

Advise as to how to post images or zip file of configs. Not working for me.

bklein Reply
Mar 20, 2023 00:00

1772_AnalogIn to ADC's to SerialOut 3-20-2023.dspproj

Oh, you click the Upload before finding a file... I was trying to paste in a filename...

bklein Reply
Mar 28, 2023 00:00

Bump...

Any chance you can run my file and verify that the ADC output direct seems dead compared to the DSP block output?

bklein Reply
Apr 20, 2023 00:00

Bump again....