ADAU1772 functionality using external MCLK and i2S data

bklein Question

Apr 14, 2023 00:00

Here are use cases my manager asked about...

We plan to run MCLK to all codecs (no local xtal or osc.) but it is undecided if it will be used - there is an unknown left that we need to understand.

Is it possible for the codec to run in PLL mode without a MCLK input? Can the chip sync to I2S data or self-boot, without an MCLK input?

Also if the codec is sending I2S data to the FPGA, does the codec need MCLK sync from the FPGA, or otherwise must the FPGA have some sort of ASRC in its design to sync to codec data?

Do you suggest LVDS drivers and transceivers for MCLK to reduce EMI? (when would this be appropriate?).

Thanks,

Barry

hardware

adau1772

Integrated/Special Purpose A/D Converters

Audio CODECs

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DaveThib Reply

Apr 18, 2023 00:00

Hello Barry,

Lots of questions,... let me give this a go.

First I assume you are calling the ADAU1772 a codec? It is a codec but with a fast DSP core as well. But I think you are clearly talking about the 1772.

bklein said:
Is it possible for the codec to run in PLL mode without a MCLK input?

No, the PLL must have a clock input otherwise it is a piece of melted sand.

bklein said:
Can the chip sync to I2S data or self-boot, without an MCLK input?

Same answer as above. You must have an MCLK.

Now, you can use the BCLK signal as an MCLK if it is the right frequency. You need a minimum of 8MHz which means you would have to be running in TDM8 or something like that. Obviously, it will depend on the sampling rate.

bklein said:
Also if the codec is sending I2S data to the FPGA, does the codec need MCLK sync from the FPGA, or otherwise must the FPGA have some sort of ASRC in its design to sync to codec data?

One of the strong points and handy features is that the serial port has ASRCs on both the input and output. So I recommend you send the clocks from the FPGA to the codec serial port inputs. Then the serial port ASRCs will just follow the rate that is coming in. Super easy.

This is why you really do not need to worry about sending the exact MCLK from the rest of the system. It just needs MCLK from somewhere. Often it just has its own crystal and works in its own clock domain. The serial ports will follow the rate coming from the FPGA.

bklein said:
Do you suggest LVDS drivers and transceivers for MCLK to reduce EMI? (when would this be appropriate?).

I do not think this is needed. Like I said above, just get an MCLK source locally. The EMI issues you are asking about is difficult for me to answer not knowing anything about your product. LVDS is certainly great for long distance runs to many cards on a backplane etc.