Instable S/PDIF output with the ADAU1463

Dear members,

The problem encountered most probably is related to a similar problem encountered previously with the ADAU1452:

ez.analog.com/.../instabel-88-khz-s-pdif-output-with-the-adau1452

I’m currently working on the firmware of a processor that incorporates the ADAU1463. One possible version “register-reads” the contents of the S/PDIF inputs and all processing is done at the default rate of this S/PDIF signal. After processing the signal is send to both the SPDIF transceiver output as well as, via an ASRC, to serial output 0 (which is connected to a DAC-IC.) The connection to the serial output and DAC-IC works fine at all standard frequencies and a proper analog signal is generated. However, when the SPDIF output is connected to an external DA-converter at some frequencies problems occur. I’ve tested more extensively with the schematics below:

Two different DA-receivers were connected to the SPDIF output. The first internally uses a WM8804 SPDIF-receiver-IC to convert the signal into I2S format to be send to a DA-IC. This one works fine at all accepted frequencies (32, 44.1, 48, 96, 192 kHz) except for 88 kHz. At this frequency the receiving WM8804 looses signal-lock several times per second.

Fortunately though for this situation I was able to find a workable solution: Changing the PLL Feedback Divider from 96 to 95 cured the problem (wit a register-write when a 88kHz signal is detected). For all other frequencies the value has to be set to 96. (Note: The MCLK-frequency was 12.288 MHz)

The second DA-receiver uses the SPDIF input from another ADAU1463 and here the real problems start. Whereas the 88 kHz is now properly recognized, even with the PLL Feedback Divider set to 96, the DA-receiver was not able to properly process the signals at 176 and 192 kHz.

The DA-converted 192 kHz signal shows short 40 ms interrupts every few seconds. The problems with the 176 kHz were more severe. There hardly any stable locking at all.

Unfortunately this time it was not possible to solve the problems by changing the Feedback Divider or changing any N / M value of the three clock generators.

I do not have a digital analyzer at hand to digitally verify the SPDIF output signal. Could it be a jitter problem?

Any suggestions???

Cheers

Jan Meier

Audio Signal Processors

adau1452

hardware

adau1463

SigmaDSP Audio Processors