ADAU1462 TDM16 Serial IO Not Working
I'm currently trying to program the ADAU1642 and I'm having issues with both reading TDM16 signals in and writing it out at 44.1kHz with 32 bits per channel. I saw a similar post made about the ADAU1643 and I'm concerned that there might be a similar issue in the ADAU1462 ADAU1463 TDM16 in slave mode
Can anyone confirm this?
Clock:
My ADAU's clock is coming from an external source at 22.5792 MHz. I have set my PLL CLK Src to 'direct from MCLK pin,' I am using a PLL input clock divider of 8. The PLL feedback divider is 104. Finally, my NxM is 1x1.
Input/Output signal:
My ADAU's BCLK and LRCLK are configured as slaves on the input and as masters on the output. The polarity on the LRCLK and BCLK inputs are positive and the LRCLK type is pulse. The output is the same, however the BCLK's polarity is negative. Each signal should be TDM16 (16 channel, 32 bits/channel) I am using SDATA0_in an SDATA0_out. The serial output sampling rate is set to fs*2.
Experimental results:
I am able to generate output when using lower TDM algorithms using a white noise generator as an input in SigmaStudios but when I pass in anything from SDATA 0-16 in, there is no data at the corresponding TDM offset.
At TDM16, the BCLK and LRCLK are no longer present on the output and I am not getting any data out.
Note:
I had to set my NxM to 1x1 and output sampling rate to fs*2 after some trial and error. At 1x1 with output sampling rate set to fs, I would get a BCLK output frequency at half of the expected 22.5792 MHz. When I set the output sampling frequency to fs*2, it fails as described in the experimental results.
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ADAU1462WBCPZ4300
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Hello YutongGu,
YutongGu said:
I have set my PLL CLK Src to 'direct from MCLK pin,'
I have noticed one thing here in this line. Here you are actually bypassing the PLL which means your system clock is same as your MCLK which is 22.5792MHz. You must select 'PLL clock' in the PLL CLK SRC register to have maximum of 294.912MHz as a system clock. That register PLL CLK SRC (0xF002) is actually not a source to the PLL but a source to the core. 22.5792MHz is much lower than the nominal rate. So, please change it as 'PLL clock' and probe and check for the presence of any BCLK and LRCLK.
Is your desired sample rate 44.1KHz? Do you intend to run the core and serial port in that rate?
YutongGu said:
The serial output sampling rate is set to fs*2.
Why are you running the serial output port twice the rate of your core? Is there any special reason for that?
YutongGu said:
I had to set my NxM to 1x1
Do you mean N/M ratio of the clock generator?
If you want 44.1K as a core rate for 22.5792MHz MCLK, then here is the setting,
Set the PLL input clock divider as 8 and PLL feedback divider as 104. And set N/M of clock generator 1 as N/M = 40/260. Now, if you can measure the LRCLK of any serial port then you will see 44.1KHz (if serial port rate is set as base_fs)
Regards,
Harish
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