ADAU1787 latency

Hi nehem,

I can take a look at your project setup in SigmaStudio and get back to you within the next day or two.

Cheers,

TM

zero_latency.dspproj

Thanks,

Attached the simple project.

I was also trying to shorten the time by setting the ADC/DAC to 768K(not in the attached) , but could not set the registers (FDEC/FINT) properly, to set SDSP to 24K.

Will appreciate your help.

nehem

Hi nehem ,

If you desire to use the path with the lowest latency possible on the ADAU1787, using the FastDSP should be the routing path you would want to setup your SigmaStudio project around.

FastDSP_Low_Latency.dspproj

Above is a simple setup for routing ADC to DAC at 768kHz for the lowest latency possible. The FastDSP should be preferred because it uses a Reduced Instruction Set, i.e., RISC architecture. Simply put, adding in processing blocks for the FastDSP will be a 1-to-1 ratio to Cycle count. So, routing your ADC through a single Filter block then to the DAC would have a total of 1 Cycle or 1 instruction, if routed through the FastDSP.

As you mentioned before and in your project setup, routing the ADC to the DAC in the SigmaDSP takes around 47 Cycles to achieve this path setup. This is because the SigmaDSP requires more overhead in order to establish its routing paths.

There are some trade-offs between the two, where the FastDSP can achieve faster processing but is limited to 64 total instructions. Likewise, the SigmaDSP can have up to 512 instructions, but at a slower speed due to the overhead cost for setting up that path.

If you were interested in learning how to properly route the FINT/FDEC, here is another example project:

ADC_to_FINT_to_FDEC_to_DAC.dspproj

This project uses the FastDSP to Interpolate the ADC Input up from 24kHz to 48kHz, then routes out of the FastDSP to the SigmaDSP where the FDEC reduces the sample rate from 48kHz back down to 24kHz and out through the DAC. This should give you a better idea on how to setup the routing if your project needs to use the FINT and/or FDEC.

However, since this routing uses both the FastDSP and SigmaDSP it doesn't matter what rates you are sampling, interpolating, or decimating, it will not be as fast as just routing the ADC through the FastDSP to the DAC. The 768kHz rate is optimized when just using the FastDSP route as in the first project I've attached.

I hope these example projects clear up some of your confusion and also help you better understand some of the routing. Take note of the Schematic block diagram connections in the Schematic tab, and also checking the routing paths by inspecting the DAC_CTRL, FDEC_CTRL, and FINT_CTRL registers in the Hardware Configuration tab for how everything is chained together.

If you have any more insight on the objective of your project or any other questions, feel free to reach back out. Hope this helps you on your current and future projects using the ADAU1787!

Cheers,

TM

Hi TM,

Thank you for clearing up my doubts regarding the FDSP-> SDSP datapath.

The ADC_to_FINT_to_FDEC_to_DAC project is very hepfull.

nehem