Slave mode of clock for PDM interface
Hello. Everyone.
Thank you for your help.
I am trying to set the slave mode of clock for the PDM interface with ADAU1787. But what I can only find in SigmaStudio is the clock for the PLL.
It will be more than help if I can get to know how to set the slave mode of the clock for the PDM interface.
Best regards
software
ADAU1787
slave mode
pdm
Integrated/Special Purpose A/D Converters
ADAU1787 evaluation board
Audio CODECs
Show More
Yeongseok,
For the ADAU1787, the PDM_CLK is only an output for the PDM OUTPUT Interface. If able to tolerate the latency, the PDM_CLK output from your PDM interface could be routed to MCLK pin on ADAU1787. The PLL would need to be adjusted accordingly. Then, the PDM_DATA from ADAU1787 could be sent back to the interface and timed on your PDM_CLK. You would need to ensure the MCLK source is the PDM_CLK from your PDM interface to keep the timing domains synchronized.
Please log in to reply.