ADAU1466 DSP BCLK PIN Configuration

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Hello AIQ,

Sorry for the delay in response.

AIQ said:
What does BCLK_OUT_PULL mean? If Pull-down enable ,does it mean pull this pin to gnd via a resistor? What its resistance value then? What the purpose of this design is?

Yes, an internal pull down is configurable for BCLK, LRCLK , SDATA pins. You can enable or disable it in sigma studio like below. The pull-down resistor is active as a default and the internal pull down will be really weak, around 150K.

Please look at the table in page18 for configurable internal pull up/down pins.

AIQ said:
BCLK_OUT_SLEW seem can change slew rate of BCLK waveform, what is it used for?

Please look at this post which has some info.

AIQ said:
In which manner the BCLK_OUT_DRIVER change different driver strength? And in which occasion should we consider use highest mode ,and does it have other effects, bad and good?

Increasing the drive strength will decrease the rise and fall times giving more timing margin to not miss any data bits. Usually, it will be used for higher sample rates like 192KHz or if you are taking more pins out from a single node which causes signal integrity issues.

AIQ said:
Could you please share us a brief snapshot of circuit or block illustration of this BCLK_OUT pin?

Do you want an internal circuit? I don't think it will be available to share.

Regards,

Harish