Analog output observation with Serial Port 0 &1

Hello KS2021,

If you look at the Eval-board schematic, you can see that BCLK_OUT0 and LRCLK_OUT0 is the only clock source which is connected to the DAC side, other serial output ports data just follow this clock. Other ports serial clock pins are going nowhere.

Hence if you change the serial output 0 clocks then it will affect all three ports data. since the data is referenced by the port 0 clocks.

If you set port 0 as TDM16 and port 1 as TDM 16 then you will hear the expected results. I mean, other ports need to be set to same number of channels that serial out port 0 is set for.

Regards,

Harish

Hello KS2021,

One other little detail to add to what Harish said. If you desire to run a TDM16 line to the converters (I would suggest TDM8 since there are only 8 DACs, but this is another discussion) You would have to set the codec to TDM16 mode. The codec is in Standalone mode which is where all the DSDATA pins are used as I2S (TDM2) inputs. You can modify the board to allow either SigmaStudio or the DSP to control the codec. I detailed this mod in the user guide for the eval board.

Dave T

Thanks for your support, Dave & Harish.

We have another observation shared below, please support.

While interfacing 2 'EVAL-ADAU1452RevBZ' boards, pop noise is observed in Analog output. During pop noise observation in listening, jump issue is observed in Spectrum domain. Please find the attached code package and output waveform. We have doubted this is due to sync in clock for Codec. Please check.

(Sinetone generator->Serial Out0 TDM2) Master Board1 -> Board2 (Serial PortIn3TDM2(Slave)->Analog Output)

PopNoise_AnalogOutput.zip

Hello KS2021,

Every sport output (port 0 provides the clocks) on the 'EVAL-ADAU1452RevBZ Board' is connected to the codec. I'm assuming that your slave board is connected in parallel to it. The noise might be caused due to an external wiring and connections. Try proceeding cautiously by using high-quality jumper wires, OfCourse the shortest and twisted grounds for each individual signals.

Below is how the sport out is connected to the codec.

Regards,

Harish

Thanks for the details, Harish.

i) Can you please share the details of what is 'high-quality jumper wires', also any purchase link for this.

ii) Even with twisted grounds for each individual signals, Tup noise is observed.

iii) Also, even with the external wiring from Master to Slave board, we have observed the SPDIF output correctly without any noise. We have doubted with the clock routing for the Codec. Please suggest verifications points in this if any.

iv)We have verified by pairing with SHARC based hardware also, still the Tup noise is observed.

SHARC as a Master for clock and Data-> Eval-ADAU1452RevBz/Eval-ADAU1466Z as a slave -> Tup noise in Codec (Serial Port 0) is observed. Please support in this.

Hello KS2021,

If both boards are not from a same master clock domain, then you must use ASRC at the input side.

I believe, SHARC has its own master clock and SigmaDSP has its own MCLK (Eval board has its own crystal), and both are not from a same domain. So, it will be out of sync.

Use ASRC at the input side of the sigmaDSP and check the results.

Regards,

Harish

Dear Harish,

Sorry for the delay, while enabling ASRC also, Tup noise issue is observed.

This could be specific with codec only, since the SPDIF output is observed correctly for the same Serial Input Port. Please support in resolving this issue.