Sending I2S from DSP to external DACs

Hello zdr,

I see you slaved off the serial port clocks to the external clocks. But it seems like the DAC that you mentioned above can't be providing serial clocks. I mean, it can't be a master and it can only be slaved. Hence you must set the serial output ports of the sigmaDSP as the master.

I need a few details.

What sample rate you are using?

Which MSB position are you using, like I2S, left justified or right justified?

Anyway, here I have shared the left-justified, 48 kHz sample rate register settings. See, the control pins are given. So set it accordingly.

The serial output port LRCLK is going to the DAC which is 48KHz.

I will also attach a basic project which simulates yours.

spdif test 1.dspproj

Kindly get back to us if you have any questions.

Regards,

Harish

Hi Harish,

Thanks for the input. I guess I am not clear on how to pass SDATA out on all 4 ports. If I select LRCLK and BCLK as masters and CLKOUT being sent out as MCLK to PCM1794, I get LRCLK and SDATA signals out correctly, but nothing is coming out of BCLK line. I would also like to keep the original sampling frequency coming in from SPDIF, and not to resample it.

Never mind, it was a bad solder joint. Only one question remains - how can I preserve the SPDIF input sampling rate and send it to the output?

Hello zdr,

This is a good question and it is a sore spot in the chip design. You can copy the clocks and data from the SPDIF input directly to the SPDIF output but that is really not useful. I wish it would be possible to add an ASRC going to the SPDIF_TX but it is not possible.

The SPDIF_TX gets its sample rate from the DSP Core Start Pulse selection. So you could set the core to run at the SPDIF rate but this means that everything else coming into the core, except the SPDIF_RX, would need to use the ASRCs.

I have this project which show you how to directly bring the audio from the SPDIF_RX into the core and the core is set to the SPDIF rate. this will make the SPDIF output rate be at the same rate as the input rate. Then I have the serial input from the codec coming from the ASRC and the output to the codec is going through an ASRC.

Note the project is labeled as using the 1452 but it is using the 1467 DLL. It will work on either sets of cores.

Dave T

ADAU1452 SPDIFDirectlyDSPCore.dspproj