ADAU1701 slave mode, move Fs from 48K to 96K
Hi!
I trying to modify my old project.
Old version, 48K ( MCLK = 12.288MHz , BCLK = 3.072MHz , LRCK = 48KHz) is working fine.
But, new, 96K ( MCLK = 24.576MHz , BCLK = 6.144MHz , LRCK = 96KHz) sounds distorted, even if ADAU1701 is used simly as bypass (image included). Sigma project is set to 96k, program size = 2x (512).
ADAU is connected to MCU. MCU could only produce MCLK = 256 x LRCK , so MCLK = 96K * 256 = 24.576M.
PLL of ADAU is set to 0. 1 => 256x.
How to make this chain working fine at 96K? Am I need PLL change, or the way is only to make ADAU master and add 12.288MHz crystal?
Audio Signal Processors
software
SigmaDSP Audio Processors
adau1701
Hello igorPie21,
I did notice one little thing in your screenshot of the registers you have it set to 192kHz.
The datasheet could certainly be better. You need to set the internal frequencies correctly and I think you are not. By using the 24Mhz crystal and the 256x setting this will cause the internal system clock to be twice as high. This will be out of timing range of the core. If it could do this then you would set the core sampling rate for 1X (1024) which would be great if it could do that and end up with 1024 instructions at 96kHz but it cannot do that.
The base sampling rate will be either 48kHz or 44.1kHz if you use a slightly slower crystal. So based on this base rate is how you set the PLL for the crystal frequency. If you keep the ~24MHz crystal then you have to set the PLL to the 512x setting because that crystal is 512x48kz. Then you set the core rate to the 2x(512) setting and it should all work fine.
Another little observation that really does not matter. We do have a signal_Invert block to invert the polarity of the signal. You are using a gain block set to multiply by -1. I have not done an analysis of instructions used but I would guess they would be exactly the same so it does not matter. It just caught my eye when I saw that.
Try changing the settings of the PLL lode and the core rate and see where you end up. There also could be some signal integrity issues associated with higher bit clock rates but that would be some clicks and pops. This is not what you described but you may run into this later.
Dave T
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Thanks for the quilck answer, Dave.
My bad, i tried all modes , 1x , 2x and 4x to get system work and posted 192K settings. It's sounded distortetd as 96K.
Phase invertions is fine, it's inverted in analog domain, so digital domain invert it back.
As far as I understood, at this situation I can't get 96K sampling rate off 24.576 masterclock at slave mode? Only 48K and 512 instructions instead of 1024, that is all because chip have no x128 PLL multiplier?
So, it looks, the only way to get 96K SR is to make ADAU1701 I2S master.
Thanks a lot!
Setting the PLL to 512x is helped!
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