POP noise observation in Analog output (Codec)

Hello KS2921,

Thanks for sending the project. I will have a look at it. I may have some more questions once I have it open and look more closely at the issue.

But there are a few questions I can think of before I open up the project.

Are you using headphones and which outputs are they connected to?

If not headphones then what are you connecting to the output?

When is this pop observed? At power up? Power down? When switching sources?

Dave T

Thanks for your support, Dave.

Please find the required details below.

Yes, we are using headphones for listening the output, connected with analog output port 16 & 17.

Pop noise is observed in default output itself (for the duration of 12 sec output 6 or 7 times mild pop noise observed), we are not switching sources. While power up and power down, this noise not observed. Please check the recorded output for the pop noise also in the code package 'Sin_48k_1k_0dB_AnalogRecording.wav'

Also, please check the codes shared in previous post and share your feedback ASAP.

Dear Dave & Team,

Please look into the above query.

Hello KS2021,

Sorry for the delay. Things have been rather busy recently.

I looked at your projects. This is a clocking issue. The two eval boards are on their own clock domain so you have to translate between these two clock domains. There are a couple of ways to do this.

Let me describe what is going on in the slave unit. You are bringing in the I2S signal that is not synchronized with the master clock on the slave eval board. There are a few ways to deal with this.

You can route the input serial port to an ASRC then bring that into the core with the core running on the internal clock domain. That would work.

Another way is to change the start pulse to synchronize the DSP core to the incoming clock on serial input port 3. So the DSP program will be running on the clock from the other board. Then the issue is going to the codec on the slave eval board. The codec is still operating from the local clocks so you would have to take the core output and send it to an ASRC then to the serial output port to go to the codec.

What I am saying is you either have to use an ASRC on the input to the core or the output from the core. The easiest in on the input side. Then you can also setup a program to mute the ASRC when it loses lock. I had uploaded a program to do that elsewhere on the forum.

The last way to do this is not easy on this eval board. I would have to break out the schematic and have a look. What you could do is disable the master clock on the slave board. Then take the CLKOUT of the master board and jumper it over to the slave board to have both boards running on the same master clock. Then no ASRCs would be required. But this would require some soldering and jumper wires. If you do this I recommend to run a ground wire along with the clock to maintain some signal integrity and they cannot be too long.

Dave T