ADAU1467 TDM8 SDATAIO configuration

MarcoSilenzi Question

Jul 8, 2024 00:00

Hello,

I'm working on a project with double ADAU1467. The block diagram is the next:

I have ADC1 and ADC2 connected in TDM8 mode to DSP0_SDATA_IN0 (4 channels each ADC), ADC3 connected in TDM8 mode (only first 4 channels used) to DSP0_SDATA_IO0. Then the signals go to DSP1 (with TDM8 ports) and to the DAC (with TDM8 ports).

The signals from DSP0_SDATA_IN0 work well, but the signals from DSP0_SDATA_IO0 are not working, the sound is completely wrong.

All the BCLK and LRCLK are connected each other (ADC, DAC, DSP): the DSP1_OUT0 port is BLCK/LRCLK master (Drive Strength Highest) and all the other ports are slave (note that the two DSPs have the BLCK/LRCLK of IN0 and OUT0 port connected each other).

The MCLK for DSP1, ADCs and DAC is generated from DSP0.

I made some tests:

- I inverted the ADCs with the same result (so all the ADC are working well)

- I used a internal sine from DSP0 as audio sample and everything works well

- If i set MCLK_OUT on DSP0 to 12Mhz everything works fine, but I need 96kHz application, so the MCLK must be 24,576MHz

It seems that the problem is the SDAIO port. Do you have any other ideas? How should i configure the ports?

I attach the project.

HMLP1214.dspproj

Thanks

Marco Silenzi

Audio Signal Processors

hardware

sdataio

adau1467

tdm8

SigmaDSP Audio Processors

HMLP1214.dspproj891.5 KB

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Harishgowtham Reply

Jul 9, 2024 00:00

Hello Marco Silenzi,

Thanks for attaching your project, it helped a lot. It seems like you configured everything correctly. I suspect the issue is something else.

There was a silicon bug with the SDATAIOx as input pins, it's missing the timing when running at higher frequencies. They work fine at the output side. Please refer the thread here. A workaround was also given in that thread.

Now I suspect your issue has to do something with the above thread. I suspect that when the BCLK is above 12.288MHz, it doesn't work properly. I quickly tested the below things, could you please try the below configs and get back to us with your results.

SDATAIOx at input side

Mode

Sample rate

Bit clock

Status

TDM4

48KHz

6.144MHz

Working

TDM4

96KHz

12.288MHz

Working

TDM8

48KHz

12.288MHz

Working

TDM8

96KHz

24.576MHz

Not working properly

TDM4

192KHz

24.576MHz

Not working properly

I tested the SDATAIOx pins as outputs, they work just fine as TDM4 at 192KHz (using serial port's full bandwidth - 24.576MHz).

So, it seems like the issue is with that SDATAIOx pins at the input side.

Could you please try the same and get back with your results?

Regards,

Harish

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MarcoSilenzi Reply

Jul 9, 2024 00:00

Thank you for the answer!

I can confirm that these tests are verified. I cannot make the other at moment.

Then I tried the workaround proposed in your link and it resolved the problem (and confirm the silicon bug)! But it halfs the maximum analog input signal and it's not acceptable in my project.

Do you know if exists another less impactful workaround? Is it possible to have an errata sheet for this product for future application?

Thanks again

Marco Silenzi

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