Serial I2S and SPDIF TX not "in sync"
Thread Summary
The user is experiencing a time alignment issue between I2S outputs and SPDIF TX on the ADAU1452, despite using the same 1kHz internal sine generator. The final answer suggests checking the scope shots and sample rate, noting that the ADAU1452 does not support the TX_MCLKSPEED register for SPDIF. The accompanying answer clarifies that a small delay is expected due to SPDIF block structure setup, and precise phase alignment is not typical.AI Generated Content
Hey forum, thanks for having me !
So in my ADAU1452 project I run the 4 I2S outputs pairs ( with 4 PCM5102 boards ) and the SPDIF TX ( with a SPDIF to ANALOG external DAC ) on the same 1khz internal sine generator.
The problem is, I see on my physical scope that the I2S outputs are not time aligned with the SPDIF TX. Is there any setting that I should take care of? I cant find the equivalent of TX_MCLKSPEED for ADAU1452 ( maybe that would solve the problem? ).
All the I2S outputs are time aligned among them, only the SPDIF has this problem.
Thanks a lot !
Audio Signal Processors
adau1452
software
4.7 1831
SigmaDSP Audio Processors
Hello mambus,
mambus said:
I see on my physical scope that the I2S outputs are not time aligned with the SPDIF TX
Could you tell us what's the difference that you measured in the scope? Can you attach the scope shots? which one you see is faster?
mambus said:
I cant find the equivalent of TX_MCLKSPEED for ADAU1452
Regarding TX_MCLKSPEED register, this is available in sigma350 cores, and it is used to run the S/PDIF at 192 kHz Sample rate. since the ADAU1452 S/PDIF does not support 192 kHz sample rate, so I think it's not there.
Are you using our evaluation board or a custom board?
What's the sample rate?
Please attach your project, so it will be easy for us to quickly look at the registers.
Regards,
Harish
Hello Mambus,
I am going to add a little to what Harish has said. I am interested to see what you are comparing with a scope? The I2S is bit clock, LRCLK and data, very different to the bi-phase mark encoded data with the block structure for all the control and user bits that makes up the SPDIF format.
What are you triggering on?
The SPDIF-TX sampling rate is derived from the core start pulse. As Harish mentioned, include your project so we can see what the start pulse is set to and what the serial port is clocking to.
There is most likely a small delay because the SPDIF hardware has to setup the block structure. There is no expectation of precise phase alignment of the SPDIF and the I2S. It actually would expect it to be slightly different. The sampling rate will be the same and the data will be the same but the SPDIF has a lot of overhead to send out.
Dave T
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