Usage of pinmux

Hi,

When a pin is in peripheral mode (not GPIO mode), the PORT_MUX register controls which peripheral takes ownership of a pin. Ports may have multiple, different peripheral functions. Two bits are required to describe every multiplexer on an individual pin-by-pin scheme.

The Signal Multiplexing table of ADSP-SC59x processor can be found in its datasheet (Pg:40/139).
www.analog.com/.../adsp-sc596-adsp-sc598.pdf

For example, bit 0 and bit 1 of the PORT_MUX register control the multiplexer of pin 0, bit 2 and bit 3 of PORT_MUX control the multiplexer of pin 1, and so on. The value of any PORT_MUX bit has no effect on the port pins when the associated bit in the PORT_FER register is 0 (selects GPIO mode). Even if a port has only one function, the PORT_MUX register is still present. For single function ports (no
multiplexing is needed), leave the PORT_MUX bits at 0 (default). For all PORT_MUX bit fields: 00 = default/reset peripheral option, 01 = first alternate peripheral option, 10 = second alternate peripheral option, and 11 = third alternate peripheral option.

Input tap functionality enables a particular pin to act as input for particular functionality without configuring any of the PORT registers(from reset values). So one can directly feed the input signals without changing any of PORT settings.
Input taps lines are implicitly selected when corresponding peripheral input enables are active.

For example, if you want to enable the UART2_RX functionality in the Port D pin 11(PD11), then the PORTD_MUX register should be set to 0x00400000 as it is the first peripheral functionality of PD11.

For more information about, please refer the PORT Multiplexing Control, PORT_MUX register and Pin multiplexing in ADSP-SC598 HRM. Please find the below link,
https://www.analog.com/media/en/dsp-documentation/processor-manuals/adsp-sc595-sc596-sc598-hrm.pdf

Regards,
Nandini C