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Data synchronization mechanism in SigmaDSP

SigmaDSP & SigmaStudio Foster Nov 6, 2024 00:00 2 replies Original on forum ↗
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Foster Question
Nov 6, 2024 00:00

Hi,

I need to know how to sync datas from other device in SigmaDSP.

Assume there are two 1452s connected using i2s, however the two 1452s use different XTALs.

Although they all run at 48KHz sample rate, two XTALs cause the difference. For examle, one is 47.99999KHz, and the other is 48.00001KHz.

Let's say two 1452s are DSP1 and DSP2, and DSP1 is a little slower than DSP2.

There are four situations we need to consider in the i2s transmit and receive.

1. DSP1 as clock master, DSP1 transmit and DSP2 receive which is slow to fast.

2. DSP1 as clock master, DSP1 receive and DSP2 transmit which is fast to slow.

3. DSP2 as clock master, DSP1 transmit and DSP2 receive which is slow to fast.

4. DSP2 as clock master, DSP1 receive and DSP2 transmit which is fast to slow.

Let's talk about the four situations one by one.

1. DSP1 is master, so DSP1 using the frequency itself, we only need to consider the DSP2 side.

In DSP2 side, DSP2 read datas faster than DSP1 prepare datas, so there would be a certain frame the DSP2 read nothing. Here is the first question.

Is the DSP2 using the last frame datas or filling zeros when there are no new datas to read?

2. DSP1 is master. In DSP2 side, DSP2 prepare datas faster than DSP1 read datas, so there would be a certain frame the DSP2 prepare two frame datas. Here is the second question.

Is the DSP2 transmit the second frame datas which is new and throw away the first frame datas which is old?

3. DSP2 is master. In DSP1 side, DSP1 prepare datas slower than DSP2 read datas, so there would be a certain frame the DSP1 prepare no datas. Here is the third question.

Is the DSP1 using the last frame datas or filling zeros when there are no new datas to transmit?

4. DSP2 is master. In DSP1 side, DSP1 read datas slower than DSP2 prepare datas, so there would be a certain frame the DSP1 receive two frame datas. Here is the fourth question.

Is the DSP1 read the second frame datas when there are two frame datas received?

Please help me to understand how the sync mechanism works.

Thanks!

Foster

Audio Signal Processors

adau1452

software

SigmaDSP Audio Processors

synchronous

DaveThib Reply
Nov 7, 2024 00:00

Hello Foster,

I first will start by giving you a pat on the back and say "Well Done!" to understand and realize that two DSPs running on two different crystals will not run exactly at the same rate! You have a lot of options and some of your options you detailed are close to some of the options you have.

As with most things in engineering, there are several ways to do things and there can be small advantages or disadvantages to these different approaches and your specific system might help you choose.

Let me start with an option you never mentioned. I suppose I should number these so you can reference these options.

1) You can change your hardware to only have one crystal to drive one DSP. Then take the CLKOUT pin from that DSP and send it to the MCLKIN pin of the other DSP. Then they will both be running at the same rate. The LRCLK edges will be slightly different because the internal counters to divide the MCLK down to the LRCLK rate will not start counting at exactly the same time but that is not a problem. They will NOT drift around from each other. When the data comes into the serial port it is transferred into a data holding buffer for an additional sample period which allows for this slight difference between data sources and will align them to the same sample period when the data goes into the core.

2) Running with different crystals as you described.

You can route the incoming data into a sampling rate converter and then into the core. This will make adjustments as the rates drift apart. The only thing I do not like about this is that the worst case for ASRCs is when the two rates are very close to the same frequencies. The numbers for the ratio become very small and that can cause problems. Our ASRCs are very good and still perform well but it is not perfect. This is what you have to do when coming in on the SPDIF input.

3) Synchronize one of the DSP cores to the sampling rate that is coming from the other DSP. These DSPs are stream based processors not block based. So it runs the program every sample period. There is an interrupt (trigger) to start the program running. This is called the "Start Pulse". You have many choices of clocks. There are several internal rates that are divided down from the local crystal. However, you can also trigger this from an external source. Any of the four serial input ports or four serial output ports. These ports must be set to slave from an external clock. Then the core will start running its program when the sample just completed and is ready to go! This may be the best thing for you to do. Just slave one of the cores to the other one. Then they will both be running at the exact same rate.

The byproduct of doing this has to do with how many instructions that can be executed during every sample period. Let me give an example.

If you have a 12.288MHz crystal and you are operating at 48kHz., then the internal core instruction clock rate will be 294.912MHz once the PLL does its magic. So 294.912MHz / 48kHz = 6,144 instructions per sample period. If the sample rate is divided down from this clock (an internal rate) then it will be EXACTLY 6,144 instructions per frame. However, if you set the sampling rate to follow the rate divided down from a different crystal then you get a difference in the number of instructions per frame and it will drift as the two rates drift. So you may have fewer instructions or greater instructions per sampling period.

This will only be a problem when you have a huge program that is using almost all the available instructions. With this DSP it is difficult to fill it up but it does happen. We do have a frame overrun monitor that you could implement to check to see if you ran out of instructions during a frame. This is another conversation.

Not knowing very much about your exact application I am guessing you would want to just set the core start pulse to follow one of the serial ports.

The Start Pulse register is register 0xF401.

Dave T

Foster Reply
Nov 12, 2024 00:00

Hi Dave,

Thanks for your answer, I learned a lot from what you shared!