External SPI Delay with SRAM

Hello GEFO,

I really want you to have a look at these below threads. In that post, Dave has experimented how much we can push, and he has explained everything in detail. You will have an idea on how you much you can utilize.

How to use External SPI Delay Module on ADAU1452 with SigmaStudio Dev.Tool? - Q&A - SigmaDSP Processors & SigmaStudio Dev. Tool - EngineerZone

External SPI Delay on multiple channels using SRAM with different delay times? - Q&A - SigmaDSP Processors & SigmaStudio Dev. Tool - EngineerZone

Regards,

Harish

Dear,

in the 2 links you sent us we could not find the answers related to our 4 questions

Hello GEFO,

I don't really think connecting four chips and 8 channel delay is possible. You can't write and read back the data from all chips within a sample period. It's impossible.

In the thread I linked you to, where Dave had a real trouble writing and reading three channels (32-bit data) within a sample period. He went up to 15MHz but still it's not good enough and the audio was noisy.

He also just used a single chip (single instance) where you can just send read/write and sub address commands once and the data will be followed. He also showed us that what will happen if he adds one more instance, The read/write and sub address commands will be doubled which will cost you so much time.

Now imagine what will happen if you have four chips and 8 channels (24-bit/channel), it's not possible to make it back within a sample period. Let me share what are the possibilities below.

The possibilities are totally depending on your PCB layout. You should check up to what MHz you can read and write without a problem. If you are having difficulties with more that 15MHz with your layout, then you can't write and read 8 channels within a sample period even the data is 16bits (considering single chip).

The real problem is that since you need a long delay you plan to use 4 chips which is the real trouble, The read and write commands must be sent to every chip every time, which will cost you so much time which drastically reduces the number of channels to be used. If your project can allow 16-bit data instead of 24-bit, then we can assume a few possibilities.

Let's consider you are using only one chip (minimal delay of a few samples) and 8 channels. Let me repeat what Dave experimented, He had a hard time implementing three channels (32-bit each) write and read with 15MHz clock. If you can increase up to 18MHz without a problem in your PCB, then you can try his packing/unpacking method to store 16-bit sample into the delay memory which will buy you some time. In that case, it may be possible to implement 8 channels 16-bit delay (considering single chip).

Two instances will make the case worse even it's 2 or 3 24-bit channels.

I will comment further if I have anything.

Regards,

Harish

Dear,

OK, but how we can calculate the limits?
ex. we use an external sram of 256Kbytes.
How many delayed channels we can use than and what is the max delay per channel? (SPI bus can works without any PCB problem at 20Mhz)

Please can we also have a answer on my question 2. (Can we obtain a list of possible memories.....)

Hello GEFO,

As far as one chip (single instance) is considered and around 18MHz clock working condition and 16bit data is assumed.

So, you have 2Mbit (256Kbytes) memory. 1Mbit is 1024x1024 = 10,48,576 bits

2Mbit is 1024x1024x2 bits = 20,97,152 bits. each address is 8 bits wide. so, 20,97,152/8= 2,62,144 memory locations (8 bit each). we need 2 memory location to store a 16-bit sample.

so, 262144/2 = 131072 samples of memory space (131072 16-bit samples can be stored, 16x131072 = 2097152(2Mbit)).

If you have 8 channels, then you can have around 16,000 samples delay per channel which is 0.333 second per channel at 48KHz.

If you try using 4Mbit memory, then it will be around 0.666 second delay per channel.

The Master SPI port supports up to 32MB memory, but you cannot buy serial SPI that large. 4Mbit is what I can find easily on the internet.

You can just try using 8 channels and 16-bit/channel with your 2Mbit memory and see if you can achieve 16,000 samples delay per channel. if you have no issues then go with 4Mbit for 0.666 second.

If you can find memory higher than 4Mbit then you can try using your 1 second delay with 8 channels.

GEFO said:
Please can we also have a answer on my question 2. (Can we obtain a list of possible memories.....)

I really can't name memories that can be used since there are so many. I haven't personally used a lot. So, you can just check for few things like IOVDD and other compatibilities like instructions/commands.

We use microchip EEPROM in our eval boards. Your 4Mbit memory is also from microchip, so this microchip memory will work fine but I haven't found anything more than 4Mbit in microchip.

Have a look at this: 66_67WVS1M8ALL_BLL-2933416.pdf

I found this 8Mbit memory online, I haven't gone thru the datasheet. You can have a look and see if it fits.

Maybe you can search for higher memory unit and send us the link, we may have a look and see if it will work with the DSP.

I will comment further if I have any correction.

Regards,

Harish

Dear,

If we got it right and we use the IS66WVS1M8ALL/BLL then we have 8 Mbit or 1Mbyte of RAM that we can use.
1Mbyte x 8 bit x 2 = 1048576 * 8 * 2 = 16.77MHz on the SPI bus + some overhead for addressing.
This is below the maximum speed of 25MHz of the SPI bus on the ADAU1467.

Now we have 16 channels of 24 bits at 48kHz.
The maximum delay per channel would be:

1048576 bytes / 3 (24 bit width) = 349525 total samples.
349525 / 16 (channels) = 21845 samples per channel or 455 ms delay per channel. (21845 / 48000)

Translated with DeepL.com (free version)

If we can use the ISS66WVS1M8ALL and the above calculations are correct then this is perfect for us.

Please confirm this

Hello GEFO,

GEFO said:
1Mbyte x 8 bit x 2 = 1048576 * 8 * 2

1Mbit is 1048576 bits and1Mbyte is 1048576*8 = 8388608 bits. You made your SPI clock calculation with 1Mbit bits by naming it as1Mbyte.

GEFO said:
Now we have 16 channels of 24 bits at 48kHz.

No, you can't have 16 channels and 24 bits/channel. You can't read and write 16 channel (24-bits/channel) within one sample period. As I have been saying from the beginning, writing and reading 4 channel (32-bit/channel) is tough with stable clock frequency of around 18MHz, but it can be done if the layout is done very well. By packing the data as 16-bits, you can have 8 channels delay. If you have 8Mbit memory, then you can have 1 second delay per channel as I explained above.

But 16 channel is just not possible, memory is not the only problem; it's the timing margin. You will have very tight margin even if you use 8 channels (16-bit/channel) at 48KHz. If your bit depth must be 24 bits, then you can go up to 5 channels (considering the SPI clock works fine at around 20MHz).

Regards,

Harish

Hello GEFO,

To add to what Harish has said. Have a look at this older post where I analyzed this in great detail to show why there is a bandwidth issue with the number of channels you can write to in a sample period.

You will not be able to do 16 channels. The length of the delay line is not as much of an issue, that is simply an address in the memory but it has to do with the number of samples that have to be written during EVERY sample period.

(+) How to use External SPI Delay Module on ADAU1452 with SigmaStudio Dev.Tool? - Q&A - SigmaDSP Processors & SigmaStudio Dev. Tool - EngineerZone

Dave T