Clock sharing for multiple I2S SDATA Outputs
Hello,
For a multichannel project I am using all 4 serial data output ports of an ADAU1466 DSP, each sending 2-Channel I2S (or potentially multichannel TDM) audio data to one of four DACs (expectig 3-wire serial audio) on another PCB, connected via a cable connection.
Since the clock-rates and port configurations shall be all the same for all ports, I was wondering if it is save to use only one set of clock lines (LRCLK, BCKL) for all 4 SDOUT data lines to reduce the amount of data lines on the cable ?
Or should I use the full set of clock lines from each serial output port, because potential syncing issues could arise, or any other problems?
Best regards,
Sebastian
Audio Signal Processors
hardware
i2s_output
SigmaDSP Audio Processors
clock_distributing
adau1466
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Hello Sebastian,
You can refer to the ADAU1466 or ADAU1452 Eval board schematics, those Eval board output port connections are done in this way. The serial output port 0 is the serial clock master to the DAC and all other three data lines from output port 1,2,3 follow this clock from serial output port 0. Since all four serial output ports have the same configuration, you will have no problem.
You can see that BCLK and LRCLK out of output ports 1,2,3 are going nowhere but test points.
Are you driving only one DAC with serial output port 0, or you are splitting the clocks and giving it to more than one DAC?
Regards,
Harish
Hello Harish,
thanks for the answer. I am planning on sending SDOUT0-3 to four individual DACs (in Slave Mode) and split the clocks from serial port 0 to drive all four of them. I guess will use some line drivers/buffers for the clocks on the other PCB with the DACs. What do you think ?
Best regards,
Sebastian
Hello Sebastian,
Since you are splitting the signal and sending it to four individual DACs which are at other PCB, I think the best way is to use line drivers/buffer to ensure signal integrity and reliable operation across all four DACs.
I hope every IC is synced with a common MCLK.
Regards,
Harish
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