PLL_CTRL0 editing should happen before PLL_ENABLE changes from 0 to 1, but sigmastudio generates code where PLL_CTRL0 is edited after PLL_ENABLE is changed from 0 to 1

Hello

We have a project utilizing the ADAU1462 and have noticed the file generation for the function "default_download_xx" where xx depends on the project name, might be wrong according to what is specified in the datasheet. I highlighted a statement in the datasheet below about the register PLL_CTRL0 saying:

"The value written to this register does not take effect until Register 0xF003 (PLL_ENABLE), Bit 0 (PLL_ENABLE) changes state from 0b0 to 0b1."

meanwhile the generated code from sigmastudio goes like this (i have snipped out irrelevant parts of the function for clarity):

PLL_ENABLE bit set to 0 on line 4

PLL_CTRL1 edited on line 5

PLL_ENABLE bit set to 1 on line 8

PLL_CTRL0 edited on line 12, after PLL_ENABLE changes from 0 to 1

This means the value of PLL_CTRL0 does not take effect, and the default value, in this case 96, is used. From my understanding this means there is no way to use non default value of PLL_CTRL0 register without either:

Manually editing the generated .h file moving line 12 up above line 8

Redo the PLL_ENABLE bit 0 to 1 sequence, which might require further manipulation of other registers to do correctly.

I have confirmed that 1. works, and have not looked much into 2.

What is the consequence of this? Any hardware setup that requires PLL_CTRL0 to be non default value will be using the default value anyways, making all clocking derrived from PLL_CTRL0 different from expected. This is especially a problem for the serial ports that derrive from the PLL clock.

When does PLL_CTRL0 use non default value? This is normally only the case when using a MCLK input that is not one of the following: 3.072MHz, 6.144MHz, 12.288MHz and 24.576MHz. Another case might be if you want to run the core at say half clock speed hoping to reduce the power consumption of the DSP hardware. I think most applications use these MCLK values, but there is also a huge list of alternative values in the datasheet table 20, which use different values as exaples.

I have confirmed this behavior in both sigmastudio rev4.7 and sigmastudio+ 2.3.0 by migrating the project, but same issue appears there aswell. The code example is from the migrated project.

void default_download_ADAU146XSCHEMATIC_0()
{
//...
SIGMA_WRITE_REGISTER_BLOCK(DEVICE_ADDR_ADAU146XSCHEMATIC_0, R8_PLL_ENABLE_ADDR_ADAU146XSCHEMATIC_0 , R8_PLL_ENABLE_SIZE_ADAU146XSCHEMATIC_0 , R8_PLL_ENABLE_ADAU146XSCHEMATIC_0_Data);
SIGMA_WRITE_REGISTER_BLOCK(DEVICE_ADDR_ADAU146XSCHEMATIC_0, R9_PLL_CTRL1_REGISTER_ADDR_ADAU146XSCHEMATIC_0 , R9_PLL_CTRL1_REGISTER_SIZE_ADAU146XSCHEMATIC_0 , R9_PLL_CTRL1_REGISTER_ADAU146XSCHEMATIC_0_Data);
SIGMA_WRITE_REGISTER_BLOCK(DEVICE_ADDR_ADAU146XSCHEMATIC_0, R10_PLL_CLK_SRC_REGISTER_ADDR_ADAU146XSCHEMATIC_0 , R10_PLL_CLK_SRC_REGISTER_SIZE_ADAU146XSCHEMATIC_0 , R10_PLL_CLK_SRC_REGISTER_ADAU146XSCHEMATIC_0_Data);
SIGMA_WRITE_REGISTER_BLOCK(DEVICE_ADDR_ADAU146XSCHEMATIC_0, R11_MCLK_OUT_REGISTER_ADDR_ADAU146XSCHEMATIC_0 , R11_MCLK_OUT_REGISTER_SIZE_ADAU146XSCHEMATIC_0 , R11_MCLK_OUT_REGISTER_ADAU146XSCHEMATIC_0_Data);
SIGMA_WRITE_REGISTER_BLOCK(DEVICE_ADDR_ADAU146XSCHEMATIC_0, R12_PLL_ENABLE_REGISTER_ADDR_ADAU146XSCHEMATIC_0 , R12_PLL_ENABLE_REGISTER_SIZE_ADAU146XSCHEMATIC_0 , R12_PLL_ENABLE_REGISTER_ADAU146XSCHEMATIC_0_Data);
SIGMA_WRITE_DELAY(DEVICE_ADDR_ADAU146XSCHEMATIC_0, R13_PLL_LOCK_DELAY_ADDR_ADAU146XSCHEMATIC_0 , R13_PLL_LOCK_DELAY_SIZE_ADAU146XSCHEMATIC_0 , R13_PLL_LOCK_DELAY_ADAU146XSCHEMATIC_0_Data);
SIGMA_WRITE_REGISTER_BLOCK(DEVICE_ADDR_ADAU146XSCHEMATIC_0, R14_POWER_ENABLE0_REGISTER_ADDR_ADAU146XSCHEMATIC_0 , R14_POWER_ENABLE0_REGISTER_SIZE_ADAU146XSCHEMATIC_0 , R14_POWER_ENABLE0_REGISTER_ADAU146XSCHEMATIC_0_Data);
SIGMA_WRITE_REGISTER_BLOCK(DEVICE_ADDR_ADAU146XSCHEMATIC_0, R15_POWER_ENABLE1_REGISTER_ADDR_ADAU146XSCHEMATIC_0 , R15_POWER_ENABLE1_REGISTER_SIZE_ADAU146XSCHEMATIC_0 , R15_POWER_ENABLE1_REGISTER_ADAU146XSCHEMATIC_0_Data);
SIGMA_WRITE_REGISTER_BLOCK(DEVICE_ADDR_ADAU146XSCHEMATIC_0, R16_PLL_CTRL0_ADDR_ADAU146XSCHEMATIC_0 , R16_PLL_CTRL0_SIZE_ADAU146XSCHEMATIC_0 , R16_PLL_CTRL0_ADAU146XSCHEMATIC_0_Data);
SIGMA_WRITE_REGISTER_BLOCK(DEVICE_ADDR_ADAU146XSCHEMATIC_0, R17_CLK_GEN1_M_ADDR_ADAU146XSCHEMATIC_0 , R17_CLK_GEN1_M_SIZE_ADAU146XSCHEMATIC_0 , R17_CLK_GEN1_M_ADAU146XSCHEMATIC_0_Data);
SIGMA_WRITE_REGISTER_BLOCK(DEVICE_ADDR_ADAU146XSCHEMATIC_0, R18_CLK_GEN2_M_ADDR_ADAU146XSCHEMATIC_0 , R18_CLK_GEN2_M_SIZE_ADAU146XSCHEMATIC_0 , R18_CLK_GEN2_M_ADAU146XSCHEMATIC_0_Data);
SIGMA_WRITE_REGISTER_BLOCK(DEVICE_ADDR_ADAU146XSCHEMATIC_0, R19_CLK_GEN3_M_ADDR_ADAU146XSCHEMATIC_0 , R19_CLK_GEN3_M_SIZE_ADAU146XSCHEMATIC_0 , R19_CLK_GEN3_M_ADAU146XSCHEMATIC_0_Data);
SIGMA_WRITE_REGISTER_BLOCK(DEVICE_ADDR_ADAU146XSCHEMATIC_0, R20_CLK_GEN3_N_ADDR_ADAU146XSCHEMATIC_0 , R20_CLK_GEN3_N_SIZE_ADAU146XSCHEMATIC_0 , R20_CLK_GEN3_N_ADAU146XSCHEMATIC_0_Data);
//...
}

To reproduce the issue:

create a project with the ADAU1462 DSP in sigmastudio or sigmastudio+

change the PLL feedback divider to anything but the default 96

make any schematic

compile the project and generate the output C files

observe that the xx.h file, where xx is the project name, contains the above mentioned order of edits to PLL_ENABLE, PLL_CTRL1 and PLL_CTRL0 registers

I am aware of this other issue 4 years ago about PLL_CTRL0. It is important for reproduciton of the problem to use a non default value of PLL_CTRL0. If the default value is used the the write to PLL_CTRL0 does not appear in the generated code files, and i think that is what this other issue has observed.

ADAU1466 sigmastudio 4.5.1 xx.h file problem : missing PLL_CTRL0 generation

Audio Signal Processors

SigmaStudio+ 2.3.0

software

Sigmastudio rev4.7

sigmaStudio 4.7

bug

SigmaDSP Audio Processors

adau1462

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