ASRC not locked

Hello Pan,

In the project named 'ok':

You set the CG1's N/M values as 1/6, which makes CG1 produce 48KHz clock and you also set the start pulse as Base_Fs (CG1 x 1 output). which effectively sets the DSP sample rate to be 48KHz (running from crystal and PLL). But SS sample rate is set as 96KHz.

Your I2S audio is coming in via serial input port 3, and that is set as clock slave. You use the ASRC4 for receiving 2 channels and set ASRC output rate as 'serial output 3' rate which is also set as slave. Here you are not syncing with the DSP core rate. I don't know what you are trying to do.

You MUST sync the audio to the DSP sample rate, to do that you use 'Use DSP rate' setting in the ASRC output rate.

Because, all your serial input ports and output ports are set as slaves, so serial ports will receive clocks from external domain. So, incoming audio must be converted to core rate, not to 'serial output rate' which is also external to the DSP. It would've been technically correct if your serial output port 3 is master (derived from internal clocks) and you used serial out 3 in ASRC, but that's not the case here. You set all serial ports as slaves.

You said your incoming clocks are at 96KHz, if you share ('Y') the input and output port clocks from a same domain (still external to DSP), you are forcing the ASRC to convert from 96KHz (input port) to 96KHz (output port), then you input samples to the core at 96KHz, but the core runs at 48KHz, missing every other sample.

If you can tell us, what are you trying to do, then we will be able to help you.

In the project named 'NG':

Same thing there as well. The DSP sample rate is 48kHz (from crystal)

You input four I2S into four ports and all are set as slaves, and you use 4 ASRC for receiving them and the ASRC output rate is set as 'serial out 3' but all serial output ports are set as slaves. As I said above, you are not syncing the audio with DSP core rate, you are using ASRC to convert serial input rate to output rate but both ports are external to DSP.

There is a slight confusion with what you are trying to do. Could you please explain your application and what are you trying to do in detail?

Are you doing any processing in the DSP? are just passing thru the audio? you just want the ASRC to convert rates and don't want to do any processing?

Please answer the questions, it would be really helpful to further assist you.

Regards,

Harish

Hello Harish

thanks for your reply.

I need to apply a cascade filters for the input stream so I need to use ASRC to convert all input streaming to a fixed rate, if I don't do this I need to input thousands of coefficients every time I set a different input sample rate. that's what I need to do.

in the OK file, I set the DSP rate as 96k and it still works fine. but the NG one no matter how I set it failed to lock in ASRC, I have used the same logic in ADAU1452 for years it works fine but don't know why I can not make it work using 1467.

looking for your kind advice.

Best regards,

Pan

Hello pan,

I guess you want your DSP to run at 96KHz, so the DSP sample rate is fixed at 96KHz right?

If it is fixed at 96KHz then there is no problem, you can calculate filter coefficients for 96KHz and input them via slave control port.

Your incoming audio streaming can be at any sample rate (up to the ASRC's capability OfCourse), like 44.1KHz/48KHz/192KHz, the ASRC will convert them into 96kHz, and the core will do the processing at 96KHz. Since the coefficients are designed for 96kHz, there won't be any mismatches (OfCourse you must set the serial port to be the same rate).

The coefficients have to work with the DSP rate and not with the varying input streaming rate. The input audio rate (changing) will be converted to DSP rate (which is fixed) by ASRC anyway. so, design the filter for the DSP rate and update them via SPI/I2C.

The DSP sample rate (set by start pulse register), serial port sample rate, sigma studio sample rate at top and ASRC output rate must be the same to make the system work properly.

If this is what you are trying to do, then your project isn't quite correctly setup.

PowerPan said:
in the OK file, I set the DSP rate as 96k and it still works fine

No, it's not. It's set for 48KHz. Please look below.

So, your application is that you are running the DSP at 96KHz, and incoming audio rate will be 44.1K/48K/192KHz and you convert it to 96KHz using ASRC, and you will update the filter coefficients (pre-calculated for 96KHz) in runtime?

If this is what you want, then I can simply create a project with required settings and send it for you.

Regards,

Harish

Hello Harish

thanks for your kind reply. I tried many times even if I just used the wrong fs then the ASRC still could lock for the OK file. but the NG file couldn't.

yes, you got me right, my goal is to let the DSP run @ 96K and the incoming source could be any sample rate.

Best regards,

Power Pan

Hello Harish:

While testing the program I found 1 peculiar problem (why me again?) N=1 and M=3, start pulse is 96k

When I set Use DSP rate for the ASRC in the routing matrix tab, lock status button is red in ASRC tab. but it could work. when I set use rate of DOUT3, lock status button becomes green.

my question is: why it failed to lock but still could work?

Best regards,

Pan

another problem occurred, when I put many biquad filters in a design, like 100, it failed to work. that's why I could not make it work for days cause the biquad filters stop the chip from responding when it should work. one is when it works, the lock status does not turn green the most important thing is the chip failed to respond.

1467-8ch_All_rates.NG.dspproj

but when you delete one filter group, it works again... Self-doubt is creeping in...

Best regards,

Pan

Hello Pan,

Looking at your project, there is one important thing I should mention. You are running the DSP core at 192KHz.

There are two main ways to set the DSP sample rate with CGs.

1) You can set clock generator for 48KHz (N/M=1/6) and set the start pulse (core rate) and serial port rate as Base_fs x 2 (now base_fs is 48KHz since you set CG to output 48KHz). Base_fs x 2 is 96KHz. You can follow this if you find it easy.

2) You can set the clock generator for 96KHz (N/M=1/3) and leave the start pulse (core rate) and serial port 'as is', i.e default setting of Base_fs (now Base_fs is 96KHz since you set CG to output 96KHz).

But what you did is a combination of both, you set the CG1's value as 1/3 which makes the CG1 to produce 96KHz, and also you set the start pulse as Base_fs*2. (Here Base_fs itself is 96KHz (since we set CG1 as 1/3), but you set Base_fs*2 will make the core run at 192KHz). So, this is not correct.

So, the above screenshot must be corrected.

I will attach a simple project which will use serial input port 0 (slave) to receive audio and sync it with core and send it out to serial out 0 port (master).

I used a little usual logic with ASRC lock bit, when an ASRC lock is lost then audio will be muted.

My input signal rate is at 192KHz; hence the ratio is 2 as shown in the readback cell.

Below is your project file that I just changed the input and output ports to work with my Eval board, it works fine. when I disconnect the input clocks, the ASRC lock is lost and when I connect it again, the lock is restored, and audio is played.

Your project does work correctly, when it's properly configured.

As I already mentioned above, you must use 'DSP rate' as ASRC output rate to sync the external rate to internal DSP rate, you shouldn't use serial out 3 which is set as slave and external to DSP rate.

Regards,

Harish

Hello Harish

I finally figured out what went wrong, inst out cause the DSP failed to work properly.

but the clock for 1467 is a little bit confusing.

Best regards,

Pan