ADAU1701 3.072Mhz High-frequency deformation
Dears：
When the customer is using ADAU1701, the 3.072MHz input from the ADC is used as the main clock for ADAU1701. High frequency distortion occurs above 10kHz. It looks like the cycle hasn't changed, but the amplitude has changed, refer to the graph.
We have done the following work for this, setting the PLL mode to 64 * FS and 1 * 1024 cycles. IIS configuration alignment。At present, it seems that there is no problem with 20-10kHz
Is it a problem with the PLL Filter, currently designed according to the datasheet.
Audio Signal Processors
hardware
SigmaDSP Audio Processors
adau1701
Hello terryyuan,
It would be good to see the project. I am assuming they are running at 48kHz based on what you said.
The PLL pins both need to be tied low which is the 64x position so that seems correct. The loop filter will not need to be changed. The way this works is that there is a divider to the PLL to always feed the PLL with a 3.072MHz signal. So the four PLL setting will be divide by 1, 4, 6, 8. This means the PLL filter does not need to be changed when using a different PLL divider setting.
From your screenshot it looks like there is an alias in the audio path. It looks like a low frequency signal in addition to the 10kHz. So I suspect the input filter in the front end of the ADC. This ADC is a current input ADC so this is a little different. What do they have for an input filter?
It is bad that the datasheet makes no mention of the ADC input filter requirements or of the amount of oversampling the converter does. I am assuming it will be the usual which is a 3.072MHz clock for the ADC which is a 64x oversampling rate. So you do not need too much of a filter but you do need to filter. Noise or power supply garbage could alias down into the audio band. The Nyquist of a 64x ADC will be 1.536 MHz so a switching regulator could cause a problem. Of course just wideband noise also could. Here is the filter on our eval board.
Dave T
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