ASRC lock

Hello Stevem,

I have quickly run your project, and it seems to be working fine for me.

I used your SPDIF input and passed it to output port 0. I used all 5 ASRCs used in your project, and I get expected value 0x1F (0b00011111)

when I removed the SPDIF cable, then I got 0xF (0b00001111) which is also expected.

when I plugged the cable again, the ASRC locks again, and the register value is 0x1F again.

and your logic circuits also work fine.

So, it doesn't seem like your project has an issue with the ASRC locking unlocking functions. However, I haven't looked at your project completely.

Do you have a stable clock at serial output 0 (set as slave to external domain)?

since you are using serial out 0 clocks as DSP core rate, it must always be active and stable for the DSP to run properly.

I will get back to you, if I find anything in your project.

Please also attach your hardware schematic.

Regards,

Harish

Hi Harish,
thanks for your respond. You should try reloading the configuration while the stream is active on the SPDIF input or on the serial input ports, in order to see that the lock status register is not consistent. In fact, if I read back that register after reloading the configuration, it shows 0 instead of 1. Essentially, it loses lock, but the system still operates correctly. Below I show the ADAU registers after reloading the configuration with SPDIF routed to ASRC0 while a signal is present, and after reading back all registers. The bit lock status of ASRC0 is not consistent.

In addition, when I start up the device and the four serial input ports of the ADAU have neither data nor clock, the ASRCs output a fixed value even though I set bit 10 of register 0xF581 to 1 (0xF581=0x40).Therefore, if there is no input clock, I would expect the ASRC outputs to be muted, but instead I get a constant value at the output of all ASRCs. Below I show the ADAU output with no input on the serial ports. Each port has a constant value.

Thanks in advanced.

Hello Steven,

Sorry for the trouble.

It seems like the 'ASRC lock bit' is sticky which means that they will not change back to "0" even if the clock is removed. They will only be set back to "0" upon reset and reprogramming of the device.

When I removed the SPDIF cable, the ASRC lock bit flipped to '0' then to '1' quickly and stays at '1'. when I re-programmed the DSP then I get the value of ASRC lock bit to be '0'. so, the bit is sticky.

I will have to double check this behavior though.

StevenNob said:
n addition, when I start up the device and the four serial input ports of the ADAU have neither data nor clock, the ASRCs output a fixed value even though I set bit 10 of register 0xF581 to 1 (0xF581=0x40).Therefore, if there is no input clock, I would expect the ASRC outputs to be muted, but instead I get a constant value at the output of all ASRCs. Below I show the ADAU output with no input on the serial ports. Each port has a constant value.

Reg this behavior, this is a known DC offset coming from the ASRC. please have a look at this post, it has a solution for this problem.

Regards,

Harish

Hello Harish and Steven,

Harish, thanks for linking to my old thread about this related issue. If I recall correctly the problem with only using the ASRC lock bit when using SPDIF is the behavior of the SPDIF PLL. When the SPDIF signal goes away, the PLL loses lock of course, but then it free runs at around 24kHz sampling rate. So this means the ASRC will see clocks and lock to it. So when you stop the SPDIF the ASRC loses lock then the SPDIF PLL settles down to a 24kHz fs and so the ASRC relocks to this rate. This is why you see a short "unlock" then it relocks. If I remember correctly the SPDIF lock bit will show there is no lock. So it is good to use both lock bits. If you lose either then the entire system is not locked to any valid signal.

I do not have time to test this myself right now.

Dave T

Hello Dave,

Thank you for joining this thread and for your valuable inputs, it makes sense now.

DaveThib said:
If I remember correctly the SPDIF lock bit will show there is no lock. So it is good to use both lock bits. If you lose either then the entire system is not locked to any valid signal.

I do not have time to test this myself right now.

I will test this and post my observation here.

Regards,

Harish

Hello Dave and Steven,

DaveThib said:
When the SPDIF signal goes away, the PLL loses lock of course, but then it free runs at around 24kHz sampling rate. So this means the ASRC will see clocks and lock to it

Dave,

You are right about this. Thanks for the info.

As you suggested, it's good to use SPDIF lock bit with ASRC lock register for implementing muting and other logics.

when I removed the SPDIF cable, ASRC lock bit stays at '1' but SPDIF lock goes to '0'. please see the screenshot below.

When I removed the I2S clock, the ASRC1 unlocks, and the ASRC lock register value becomes '1'. So, the ASRC lock register is NOT sticky, it works as expected with serial port clocks.

Hi Steven,

Instead of reading ASRC registers by clicking 'read all registers' in GUI, prefer register read blocks to read the status.

Regards,

Harish

Thank Dave and Harish for the answers,
For now, I solved the issue with the DC value of the ASRCs using a DC blocking.
However, I would like to use a volume control like the one Dave suggested in this post.
At the moment, I don’t have the possibility to test with my device to check whether the ASRC lock status bit gets stuck when the system is restarted while the clocks are already present on the ADAU serial ports.
As soon as I can run further tests, I’ll let you know. Thanks for the support.