Issue with external MCLK
Thread Summary
The user encountered a low bitclock issue on the ADAU1467's serial outputs when using an external 24.576 MHz MCLK. The solution is to use the PLL clock instead of 'Direct from MCLK' for the system core clock, ensuring the core runs at the nominal 294.912 MHz. This setting is critical for both crystal and external MCLK configurations.AI Generated Content
Dear Community,
I am experiencing a weird issue with the clock settings setting up an ADAU1467. When I apply an external 24.576Mhz clock to the MCLK Pin the bitclock I see on the serial outputs is too low by a factor of 12.
If I use the same DSP program with a 12.288Mhr crystal everything works fine and as expectet.
At first I thougt my external clock might have a bad signal integrity, but then I checked the CLK_OUT signal and it is exactly as expected in both cases. Also the "PLL locked" is green. Therefore I assume the core is running at the correct frequency. However the serial ports and run at this very low speed.
I attached the two test programs and screenshots of my logic analyzer for your reference. As far as I can see the programs are identical except the prescaler and the Clock input setting.
Is there anything I overlooked? This is the first time I am working with an external MCLK.
Best regards
Alex
MCLK_int_test.dspprojMCLK_ext_test.dspproj
Edit Notes
Added information regardin PLL lock
[edited by: AST at 10:29 PM (GMT -5) on 22 Nov 2025]
Audio Signal Processors
software
adau1467
sigma studio 4.7
SigmaDSP Audio Processors
external MCLK
Show More
Hello AST,
Here is the problem,
You must NOT choose 'Direct from MCLK' option. Whether you are using a crystal or Ext clock, it must always be PLL clock.
I can clearly understand the confusion, because that register is not quite correctly named, it's not the source to the PLL but the source to the system core clock. If your MCLK is 12.288MHz and you choose 'direct from MCLK pin' then you are running the core about 24 times lower than its nominal clock speed. Its nominal clock speed is 294.912MHz. Since your MCLK is 24.576MHz, you are running 12 times slower than the nominal core clock of 294.912MHz.
when you set 'direct from MCLK' then you are bypassing PLL and your system core clock is your actual MCLK, and the CG derivations will be based on the MCLK input, hence it will be very slower.
Below is the correct setting for both crystal and direct external MCLK,
This will fix everything.
Regards,
Harish
Hello Harish,
thank you for the quick reply. That did the trick. It is working now as expected.
Best regards
Alex
Please log in to reply.