strange behavior of the clock management of ADAU1452 of years 2020 and 2025
After 2 days of debugging the "loop overrun" error, I found a strange thing.
The chip of the year 2020 is working correctly with a particular project with correct (in respect to the data sheet) clock management settings.
But, to run that project on the chip of the year 2025, it is necessary to set an incorrect (in respect to the data sheet) input divider setting, 2 times less, to increase the inner main clock, virtually, 2 times.
Now, the project is running without "loop overrun" error on 96 kHz using all available 3000 cycles on the chip of the year 2025.
Is this something known?
Audio Signal Processors
adau1452
hardware
SigmaDSP Audio Processors
Hello Raimonds,
First, what is the entire part number of both parts you are referring to?
No, there has been no silicon changes to the ADAU1452 since it was released. I did do a large datasheet update back in 2018. You can see what sections were changed in the Change History in the Rev D datasheet.
Look at page 6 of the datasheet for more info. Here is part of it:
I do not recall exactly when we came out with the ADAU1452-150 but it was requested to have a part with lower power dissipation like the ADAU1450 but also include the SPDIF.
So you will see that both of these run at half the rate internally. If you adjusted the clock dividers in the PLL it may not be good. I would have to see the details.
Then we came out with the ADAU1452K which is a consumer temperature grade specification but the rest is all the same therefore, I do not think you are using this one.
Dave T
Thanks, Dave, for pointing to the "150"!
Yes, it is about that. The chip of "2025" is "150".
And I am pushing it to work on 294 MHz to make 3000 cycles at 96 kHz.
The "D" version of the data sheet states that 147 MHz is the maximum for 150 one.
How is it to run it on 294 MHz?
Does power dissipation depend on how many cycles are actually in use?
Thanks,
Raimonds
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