Odd problem with LRCLK
Thread Summary
The user is experiencing issues with audio not passing through the ADAU1452 DSP when using a TDM8 LRCLK with a 1:7 duty cycle. The final answer suggests that the DSP's serial port in pulse mode uses the falling edge of LRCLK to signal the start of a new frame, and a 50% duty cycle with positive polarity should be used to ensure correct data alignment. The user confirms that changing to a 50% duty cycle LRCLK resolved the issue, and they are working on a plug-in card compatible with Dante, Ravenna, and Milan network audio protocols.AI Generated Content
Hi,
we have a product that used an ADAU1452 DSP processor and we are experiencing an odd problem with the LRCLK that we are sending into and using as a reference for, the SERIAL PORTS.
Firstly, I see in the data sheet that LRCLK_MODE explicitly defines either a "50% duty" cycle or a "Pulse with a width equal to one bit clock cycle" so I accept that any fault lies with our design and not your chip, we are taking steps to fix it - but engineers curiosity takes over and wants to know what is going on!!
Basically our design has audio from a network card in the form of TDM8 streams, where the card provides LRCLK, BCLK and data (256 bits, 8 channels of 32-bits per channel with 1-bit I2S offset)
The people who designed the network card have decided to generate a LRCLK that was '1' for the first channel (i.e. 32 clock periods) and low for the remaining 7 channels (We have asked them to change their design to provide a 50% duty cycle instead so that the overall product design can progress).
The issue is that with this particular LRCLK no audio seems to pass through the ADAU DSP device!!
My question is really for someone who knows how the internals of the ADAU1452 work (Dave Thib - this sounds like one for you!!) and to ask, does this sound like something you would expect or should I be looking for another problem that is stopping the Audio ?
We feed the LRCLK to LRCLK_IN0 and LRCLK_OUT0 (and BCLK of coarse) so that all of the Ports can be referenced to them. We also use LRCLK_IN0 as the Core Start Pulse.
The Core Program is running because it is flashing an LED as a heart-beat, it would therefore seem that the SERIAL PORTS really don't like this 1:7 ration LRCLK
Thanks for any comments
PhilipJ
Audio Signal Processors
adau1452
hardware
lrclk
SigmaDSP Audio Processors
Hello PhilipJ,
Yes, give the people who designed the card a hard time!! LOL. By the way, you did an awesome job describing this and giving a lot of info in very few words!! Also, you do understand a lot of this, I can tell, also, we have corresponded through the years!
Yes, you have to "know" what the DSP serial port is looking for in each mode and what it ignores.
I assume this pulse you are using is a positive going pulse that stays high for one channel slot. So I am going with that assumption.
What is happening is that the rising edge is used in some way in the DSP to signal the start of the new frame but in a way not really. Because the bit under it is from the last frame! So in pulse mode with a 1-BCLK delay, the rising edge of the LRCLK is pretty much ignored and the falling edge is what is used! Your observations are correct. It needs to be one BCLK cycle wide.
Now, another little tidbit from my understanding, and I have not tested this much, but when it is set to 50/50 mode. Then it is forced to look at the rising edge and then it ignores the falling edge!
So if you set the DSP to be 50/50 duty cycle with a positive polarity. It should see the start of the pulse that is one channel wide and it will start from there. Wait the one BCLK cycle etc. Then it will ignore the falling edge. It does not signal it to change to a different channel numbers. Like for TDM-8 from channel 3 to channel 4. (starting from channel 0)
So for an experiment try that. It may indeed work with no need to reprogram the network card.
The only strange thing is that I would have expected you would have gotten something... Just not the correct data in the correct slot and one channel in the wrong frame.
Now, for the Start Pulse, it would just be looking for the positive rising edge when set to a positive pulse. So this is why it seems like the core is running and being triggered.
Dave T
Hi Dave, your reply is exactly what I was hoping for :-)
The Network card developer has already changed to a 50% LRCLK so everything is moving ahead but it is nice to know how someone else has developed a "TDM8 synchronizing mechanism". I have had to do similar things in an FPGA so you can imagine my mind was swirling around thinking "how could this be affected so much..."
Anyway thanks for your reply, and ALL the replies you have supplied in the past, we have been able to build some great products using the ADAU chips (and your help) !!
In case you are interested - there are 3 different "network audio" protocols that we are working with, that is Dante, Ravenna and this new one called Milan. We are working to produce a plug in card that has the same footprint and specification as the Dante/Ravenna cards so that OEM product designers have basically a plug-in choice of which network they want to use. Therefore getting the Milan card to produce exactly the same clock as the other cards (50%) really was a necessary step for us.
Kind regards
PhilipJ
Hello Philip,
Thanks for the kind words. Glad you are making progress. Yes, send me a PM with details of the cards you have designed. It may be handy to know to pass on to other customers who might need it for a product but would like to not have to take the time to design the entire interface.
Dave T
My understanding is that the industry originally defined LRCLK for stereo pairs, such that a 50% duty cycle makes sense. However, when those stereo standards were expanded to 4-channel and 8-channel revisions, the "LRCLK" became an indicator for Channel 0, versus other channels. For stereo, there is only channel 0 and channel 1, so 50/50 is proper. For quad that would be 25/75, and for octal it would be a 12.5/87.5 ratio.
As with many protocols in the audio industry, half the companies do it one way, and half do it the other way.
In other words, the design engineers were not *wrong* - they simply are not compatible with the ADAU14xx processors. If interfaced to other digital audio systems, the original design would have worked fine.
Since SigmaDSP supports either I2S or TDM, I'm surprised that the LRCLK pulse width does not change according to the selected mode. I believe that I read that I2S only supports stereo (whereas other vendors support I4S and I8S, up to I32S when using 4 data lines).
Hello SoundConsulting,
I2S is a clearly defined standard for stereo and only stereo, with a 32 bit wide slot, one BCLK delayed from the start of the frame and a 50/50 LRCLK with the Left low and the right high if I recall correctly? So since it is well defined everyone does it the same way.
Well, for TDM it is the wild wild west of data transmission formats!! I have not seen the format you describe where the LRCLK is high only for the first channel. But, I understand that someone might do that. The number of bits in a channel slot is also variable. I have seen 16 bits, 24 bits and 32 bits. Usually the number of channels is even as in 4/8/16 but nothing is stopping people from doing something else!!
So we have just done a pulse mode. With a one-bit wide pulse. However, since we just look at the initial rising edge then if it is one bit click pulse wide or an entire channel it really does not matter if you only look at the rising edge. So that is how we get away with accepting some of these other formats.
This just adds to all the fun we deal with on a daily basis!! LOL
Dave T
Please log in to reply.