Transmitting S/PDIF data on DIA1 utilizing Clocking from DIA0

I currently am utilizing SPORT0 to receive audio data from an ADC on SPORT 0A and transmit audio data to an DAC based on the same external clocks on SPORT 0B. Clock rates are:

MCLK: 24.576MHz (DIA_PB03)

BCLK: 3.072MHz (DIA_PB05)

FS: 48KHz (DIA_PB04)

I have verified the clocking, and I am able to receive and transmit audio data correctly.

I am now trying to add audio data transmission vi SPDIF1 over DIA1_PB01. I have configured SPORT 4B as a transmitter and utilized the external clocking to drive both SPORT 4B and PCG0 C and D to generate HFCLK for the SPDIF1 TX. I have set up the DMA exactly the same for both SPORT0B and SPORT4B and I am using two different DMA callbacks to trap and count ADI_SPORT_EVENT_TX_BUFFER_PROCESSED events. The SPORT4B callback is executing at 1/3 the rate of SPORT0B. Below I am including my SRU and PCG configuration code. As this current setup is not producing usable output on the SPDIF1 output, I would appreciate any feedback you can provide:

void SRU_Init(void)
{
*pREG_PADS0_DAI0_IE=0x1ffffe;
*pREG_PADS0_DAI1_IE=0x1ffffe;

SRU(DAI0_PB05_O,SPT0_ACLK_I); /*ADC-DAC clock to SPORT 0A*/
SRU(DAI0_PB05_O,SPT0_BCLK_I); /*ADC-DAC clock to SPORT 0B*/
SRU(LOW,DAI0_PBEN05_I); //Making DAI pin as Input

SRU(DAI0_PB04_O,SPT0_AFS_I); /*ADC-DAC FS to SPORT 0A*/
SRU(DAI0_PB04_O,SPT0_BFS_I); /*ADC-DAC FS to SPORT 0B*/
SRU(LOW,DAI0_PBEN04_I); //Making DAI pin as Input

SRU(SPT0_BD0_O,DAI0_PB01_I); /* SPORT 0B to DAC*/
SRU(HIGH,DAI0_PBEN01_I); //Making DAI Pin as Output

SRU(DAI0_PB02_O,SPT0_AD0_I); /*ADC data to SPORT 0A*/
SRU(LOW,DAI0_PBEN02_I); //Making DAI pin as Input

//Routing for the SPDIF and SPORT 4B start here

SRU2(DAI1_CRS_PB05_O, SPT4_BCLK_I); /* codec BCLK (DAI0_PB05 cross-domain) -> SPORT4B clock */
SRU2(DAI1_CRS_PB04_O, SPT4_BFS_I); /* codec FS (DAI0_PB04 cross-domain) -> SPORT4B FS */

/* SPDIF1_TX_CLK_I, SPDIF1_TX_HFCLK_I, SPDIF1_TX_FS_I set in SPDIF_PCG_Init() */
SRU2(SPT4_BD0_O, SPDIF1_TX_DAT_I);
SRU2(SPDIF1_TX_O,DAI1_PB01_I);
SRU2(HIGH,DAI1_PBEN01_I);

/* SRU routing: connect MCLK (DAI0_PB03, via cross-domain path) to PCG inputs */
SRU(LOW,DAI0_PBEN03_I); //Making DAI pin as Input
SRU2(DAI1_CRS_PB03_O, PCG0_EXTCLKC_I); /* MCLK for PCG_C external clock input */
SRU2(DAI1_CRS_PB03_O, PCG0_EXTCLKD_I); /* MCLK for PCG_D external clock input */

/* SRU routing: connect PCG outputs and SPORT4A signals to SPDIF1 TX inputs */
SRU2(PCG0_CLKC_O, SPDIF1_TX_HFCLK_I); /* 12.288 MHz SPDIF1 biphase clock */
SRU2(PCG0_CLKD_O, SPDIF1_TX_CLK_I); /* 3.072 MHz SPDIF1 bit clock */
SRU2(SPT4_BFS_O, SPDIF1_TX_FS_I); /* SPORT4A FS (48 kHz) SPDIF1 FS */

}

static void SPDIF_PCG_Init(void)
{
ADI_PCG_CLK_INFO clkInfo;
ADI_PCG_FS_INFO fsInfo;

/* PCG_C: MCLK / 2 = 12.288 MHz (SPDIF1_TX_HFCLK_I, 256 x Fs) */
clkInfo.eClkInput = ADI_PCG_CLK_EXT;
clkInfo.nDiv = SPDIF1_PCG_HFCLK_DIV;
clkInfo.bExternalTrigger = false;

/* FS output from PCG not used for SPDIF; configure with a benign inactive setting */
fsInfo.eClkInput = ADI_PCG_FS_EXT;
fsInfo.nDiv = 256u;
fsInfo.nPulseWidth = 1u;
fsInfo.nPhase = 0u;
fsInfo.bExternalTrigger = false;
fsInfo.eFsBypassMode = ADI_PCG_FSBYPASS_MODE_NORMAL;

adi_pcg_Init(ADI_PCG_DEV_C, &clkInfo, &fsInfo);

/* PCG_D: MCLK / 8 = 3.072 MHz (SPDIF1_TX_CLK_I, BCLK) */
clkInfo.nDiv = SPDIF1_PCG_BCLK_DIV;

adi_pcg_Init(ADI_PCG_DEV_D, &clkInfo, &fsInfo);
}

ADSP-21569

spdif

hardware

ADSP-21565

processors and dsp

Processors and Microcontrollers

sport

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