SDATAIOx is not working

I post a summary of the issue as a supplement.

■ Issues
- Data input/output works from SDATA_OUTx and SDATA_INx, but not regarding SDATAIOx.

■ Things Checked
- External Clock settings and waveform timing used by each port (SDATA_OUT and SDATA_IN are operating correctly by referencing the external clock)
- When using I2S with both SDATAIO and SDATA_IN referencing the same port, set the Channel Count setting to 4 instead of 2
- Internal Channel number used by SDATAIO (SDATAIOx Pin Channel Options)

■ Test Environment
- Device Used: ADAU1467WBCPZ300
- SigmaStudio+ ver.2.3.0

Hello small man,

Please refer to the attached project below.

I have drawn your SDATAIOx part in a separate project and it works as expected.

Since SDATAIO4 is used for input port 2 in my eval board, I can't do your exact setup of configuring SDATAIO0 for port 2.

So, I used port 3 for the input from SDATAIO0. you can just refer the register config and go ahead with your setup.

SDATAIO2 is used for output with port 2.

I can see that the I2S signal coming in from both of my SDATAIOx (SDATAIO0 and SDATAIO4) pins in the meter and I can also see in the scope that the SDATAIO2 outputs an I2S signal.

Now onto your project setting,

You have configured serial input and output port 2 to 'slave from clock domain 0' which means those ports run at TDM8 mode since port 0 is getting TDM8 clocks from main DSP but your port 2 is configured for I2S, here is the mismatch.

In my attached project, I used serial port 2 to 'slave from clock domain 2' and serial port 3 to 'slave from clock domain 3' and my incoming clocks to port 2 and port 3 are I2S clocks, hence my setup works fine.

Please try this attached project in your hardware and get back to us.

6675.SDATAIOx working.ssprj

I also recommend you use the latest version of SS+ which is SS+ 3.3.0

Regards,

Harish

Dear Harish san

Thank you for your reply.

I checked with project file that you sent. The test environment has been updated to SS+ 3.3.0.

AudioCLK is supplied from an external Gen circuit, and LRCLK and two BCLKs (64fs, 256fs) are synchronized.

The CLK hardware connection is as shown in the diagram below, so CLK domains 2 and 3 are not referenced.

I2S: LRCLK=domain 0, BCLK=domain 0

TDM: LRCLK=domain 0, BCLK=domain 1

#Although CLK domains 2 and 3, which you recommended, are not used because they do not have clock inputs, SDATA_IN and SDATA_OUT are synchronized well with both TDM and I2S with CLK domains 0 and 1.

Why is only SDATAIO not working properly?

When I check with the meter, the audio input from SDATAIO is not working.

Even when I assign the OSC output to the SDATAIO output, there is no digital data output.

Hello small man,

I have simulated your exact setup, and it seems to be working fine for me. I have used SS 4.7 for this quick test. You can try this SS project and once it works fine in your hardware, I will port this into SS+ 3.3.0.

I have used input port 3 for SDATAIO0 pin since input port 2 is already used in my eval board. You can just refer the settings for your port 2.

Clocking is setup exactly like your project, except the pulse mode setting in port2/3.

I have connected same rate of clocks to the respective ports as given in your block diagram.

You can see that the SDATAIO0 is carrying an I2S signal and it's getting into the core.

I have also probed SDATAIO2 pin configured with output port 2 (Ch 36-37) and can see an I2S signal going out.

sdataiox_ss.dspproj

So, your setup works fine with this SS project. Please try it in your hardware.

If possible, please attach your hardware schematics.

Regards,

Harish

Dear Harish san

Thanks to you, the problem has been solved.

#It worked fine in the SS 4.7 environment, but not in SS+ 3.3.0. (I've attached the SS and SS+ project files.)

#The channel descriptions in Datasheet Table 35 seem to be incorrect.

Ex: When using I2S SDATA_IN2 and SDATAIOx on Port 2,

the Datasheet states that channels 32, 33, 36, 37 are used.

In reality, they are assigned to channels 32, 34, 36, 38.

I think there may be a bug in SS+ or an error in the specifications document.

ES0_SS+_20260402.ssprjES0_ss_20260402.dspproj

Hello small man,

I'm glad that it worked.

small man said:
#It worked fine in the SS 4.7 environment, but not in SS+ 3.3.0. (I've attached the SS and SS+ project files.)

I will look into this.

small man said:
#The channel descriptions in Datasheet Table 35 seem to be incorrect.

Ex: When using I2S SDATA_IN2 and SDATAIOx on Port 2,

the Datasheet states that channels 32, 33, 36, 37 are used.

I don't think that's incorrect,

The stereo SDATAIOx slot for port 2 is CH 36-37, we have been using it all the time and the ADAU1467Z eval board enables additional stereo input with this port 2 and it always appears at the right channel slot of Ch 36-37.

The Ch 32-33 is used for primary pin (default) SDATA_IN2 in stereo mode.

small man said:
I think there may be a bug in SS+ or an error in the specifications document.

There is no error in the document, I will look into SS+.

Thanks for your reply.

Regards,

Harish