Latency Details for Sigma DSP
Thread Summary
The user inquired about the system sample delay (latency) for Sigma DSP processors when handling audio data through the serial port and ASRC path with different sampling rates. The final answer indicates a typical latency of 6-7 samples for serial port operations (without intentional delays) and 1ms ASRC group delay for upsampling from 48 kHz to 192 kHz. For Sigma100 (ADAU1701) chips, the total delay for TDM serial port operations is three samples.AI Generated Content
Dear Team,
For the Sigma DSP processor would like to understand the overall system sample delay in the following cases:
1. When receiving and transmitting audio data through the serial port.
2. When receiving audio data through the ASRC path(with input at 48 kHz and output at 192 kHz) from an S/PDIF input.
Could you please provide details on the expected sample delay (latency) for these cases, along with any factors that may influence it.
Thank you,
Best regards,
Chris Shirley
software
Hello Chris Shirley,
I hope you use Sigma300/350 DSPs which are ADAU145x/ADAU146x.
This thread will give you an idea about the digital in and out latency of the processor, it's usually 6 to 7 samples (of course without any intentional delay in the signal chain), the breakdown for this 6-7 sample is explained in the thread. This thread is for ADAU1452, but it applies to ADAU145x/ADAU146x series.
Reg your second question, The ASRC group delay calculations are given in the datasheet.
In your case, it will be 1ms (fs_out>fs_in) for ASRC group delay and then the applicable breakdown given in the above thread follows.
Regards,
Harish
Hello all,
For those using Sigma100 (ADAU1701) chips, the total delay going into a TDM serial port and out again is three samples. We produce a 12-in, 4 out mixer with six -1701s, and the worst-case delay when the needed signal is five chips away is 15 samples.
Best regards,
Bob
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