ADSP-SC835 with RTL8211f not reaching 1Gbps
Hello,
We have our custom hardware that includes an ADSP-SC835 and a RTL8211f, and we are developing the firmware in CCES 3.0.3, where the ARM core is running FreeRTOS for controlling ethernet communication.
Using development boards (ADSP-SC835-SOM and SOMCRR EZlite - with ADIN1300 controller), we already validated our main firmware working perfectly at 1 Gbps, after applying your suggestions.
We adapted our firmware to run in our custom hardware, modifying everything that is specific for the RTL8211f (and not for ADIN1300), and our system is unable to negotiate 1 Gbps with any router or network device. We can succesfully negotiate 100 Mbps and 10 Mbps, but when the link is stablished at 1 Gbps, it immediately falls down after 2-3 seconds and re-negotiate at a lower speed. Then the communication works perfectly, but only at 100 Mbps or 10 Mbps.
We already examined all the hardware design and layout, and everything seems to be aligned with the RTL8211f datasheet recomendations.
Do you know if there might be any limitation from the SC835 side to work with this ethernet controller? or any other recomendation you could give us?
Thank you,
Leopoldo Budde
hardware
ethernet
rtl8211f
SHARC-FX
processors and dsp
Interface Transceivers & Isolators
Processors and Microcontrollers
ADSP-SC835
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Hi Leopoldo,
Thank you for your inquiry.
We understand that the firmware works correctly at 1000Mbps on the ADSP-SC835 SOM/EZ-LITE platform using the ADIN1300 PHY. After migrating the design to your custom hardware with the RTL8211F and making the required PHY-specific software changes, the link negotiates at 1000 Mbps, but drops after a few seconds and falls back to 100 Mbps.
Please provide your comments on below points to help us narrow down the issue.
1. Since your application runs on the ARM core, could you confirm whether you have verified the application on the same ARM core using the SC835 EZ-KIT?
2. Since 10 Mbps and 100 Mbps operate correctly, one possibility is an RGMII timing configuration issue.
The SC835 Hardware Reference Manual describes two supported approaches in this section "RGMII Board Design Recommendations":
The PCB introduces approximately 1.5–2.0 ns delay on the RGMII clock trace. In this case, the PHY should not introduce an additional internal delay.
Alternatively, if the PCB uses matched RGMII trace lengths, the PHY should be configured to introduce the required internal clock delay (this is the approach used on the ADI EZ-Kits).
Could you please confirm which approach your hardware uses? If the design relies on the PHY for the delay, could you also verify whether the TXDLY/RXDLY settings in the RTL8211F are configured as intended?
Waiting for your reply.
Best Regards,
Santhakumari.V
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