Using S/PDIF Auxiliary Output Mode
Hi,
I am trying to use the S/PDIF Auxiliary Output Mode for a slightly unusual result. Basically I am trying to bypass the use of an ASRC...
A customer has asked if our product can accept AES3 input WITHOUT using an ASRC - we have always used one to compensate for the incoming AES3 SampleRate being not exactly the same as our DSP core rate _BUT_ this customer assures us that they know why this is required and they assure us that the transmitting unit will be "hard-locked" to the System Sample Rate. As they are a highly respected Recording Studio in West London, we have to accept that they know what they are talking about and will absolutely comply with the very strict requirement of "locking everything to House Clock".
Anyway, I am feeding the incoming AES3 waveform to the ADAU1467 SPDIF input pin and I have programmed the chip to feed the decoded data out of SDATA_OUT1 using the S/PDIF Auxiliary Output Mode. I can then feed this TDM8 back to the DSP (via our FPGA) to be further processed and added to our final audio output.
My problem is that this TDM8 stream from SDATA_OUT1 does not appear to be synchronized to the LRCLK that I am sending to the DSP.
We have always done our designs such that we feed clocks to BCLK_OUT0/LRCLK_OUT0 and also to BCLK_IN0/LRCLK_IN0 then all SERIAL_PORTS are configured to be "sl@ve from CLK domain 0" so that all the TDM8 streams are synchronous to a single "House Clock" frame and bit rate.
Is it possible to have SDATA_OUT1 supplied with data from the S/PDIF decoder but clocked and synced from this CLK domain ?
I note in Sigma-Studio that there are 2 options:
---- Use S/PDIF internally derived SPDIF BCLK/LRCLK --- I have selected this one
---- Use filtered BCLK/LRCLK from clock generator --- If I choose this one the data goes weird, seaming to repeat in all 8 channel slots of the TDM8
Can anyone advise the correct way to setup the S/PDIF and the SDATA_OUT to get the data out so that it conforms to what is described in Table 46 of the data-sheet (ADAU1463/ADAU1467 Rev. A)
Thanks in anticipation
PhilipJ
PS: your website stopped me from posting this at first because I included a word "sl@ve" (but with the actual letter 'a' in it. Since I copied this phrase directly from your SigmaStudio UI it seems a bit stupid!! Perhaps you should be consistent "Words Matter"
spdif
hardware
adau1467
processors and dsp
Processors and Microcontrollers
Hello PhilipJ,
SigmaDSP doesn't meet AES3 professional specification.
Reg the clock routing, did you try this below option?
Please try this and get back to us.
Please provide a block diagram of your system clocking, it would help us understand and suggest better ideas.
Regards,
Harish
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