Does SigmaDSP perform SCLK stretching for timing sync with USBi?

After some reliability issues with SigmaStudio ReadBack (both EVAL and custom hardware, alike), I am looking at the USBi bus in SPI mode with a logic analyzer, and it appears that the SigmaDSP might be using clock stretching to coordinate with SigmaStudio, but I was not aware that SPI supported this.

I see the exact format described in the data sheet:

An 8-bit SPI address (0x00 for Read / 0x01 for Write)

A 16-bit SigmaDSP internal subaddress (memory or register)

A 32-bit value (on MISO for Read / on MOSI for Write) [actually, some accesses are 8-bit]

The only unexpected aspect is that there is a large timing gap between address and value, as if the SigmaDSP is holding SCLK until it is ready to drive MISO. Does the USBi driver insert a delay between address and data for Read operations? ... or does the SigmaDSP stretch SCLK during Read to control the timing?

If USBi is inserting a delay, then where is this exact time requirement documented? Figures 35 and 36 in the data sheet imply that SCLK does not pause between the Write of Address and Read of Value.

... or is this timing gap that I see superfluous? i.e. Not something I would need to recreate when controlling the SigmaDSP from another microprocessor.

hardware

processors and dsp

adau1463

USBi interface

Processors and Microcontrollers

spi delay

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