ADAU1787 current consumption in software power-down when using the internal DVDD LDO

We are characterizing the power consumption of the ADAU1787 in a battery-powered embedded platform. During these tests, we observed a large difference between hardware power-down and software full-chip power-down when the internal DVDD regulator is used.

In our design:

AVDD and HPVDD are approximately 1.8 V.

IOVDD is approximately 1.85 V.

REG_EN is tied to AVDD.

The internal LDO therefore generates the 0.9 V DVDD supply.

An external 24.576 MHz oscillator is connected to MCLKIN.

The measurements below were performed on a functional prototype.

We compared the following states.

1. Hardware power-down

PD held low.

ADAU1787 supply rails remain present.

No I²C access or SigmaStudio download.

2. Software full-chip power-down

PD released high.

100 ms delay after releasing PD.

No SigmaStudio program is downloaded.

All register writes are verified by I²C readback.

The final register values are:

CHIP_PWR = 0x14
ADC_DAC_HP_PWR = 0x00
PLL_MB_PGA_PWR = 0x00
DMIC_PWR = 0x00
SAI_CLK_PWR = 0x00
DSP_PWR = 0x00
ASRC_PWR = 0x00
FINT_PWR = 0x00
FDEC_PWR = 0x00
KEEPS = 0x00
This corresponds to:

POWER_EN = 0
MASTER_BLOCK_EN = 0
CM_KEEP_ALIVE = 0
KEEP_SDSP = 0
KEEP_FDSP = 0
XTAL_EN = 0
DLDO_CTRL = 01 (0.9 V)
CM_STARTUP_OVER = 1
3. Active mono audio processing
For comparison, we also tested the device with one analog input, the SigmaDSP and one DAC output active. Unused converters, serial ports, ASRCs, the FastDSP and other unused blocks were disabled.

Bluetooth, I²S and the microcontroller network core were disabled in all these firmware profiles.

Measured total board current

ADAU1787 state
VBUS: 4.99 V
VBAT: approximately 3.70 V

Hardware power-down (PD = 0)
9–10 mA
11–12 mA

Software power-down (PD = 1, POWER_EN = 0)
33 mA
38 mA

Active mono audio processing
33 mA
41 mA

These values are measured at the system input and therefore include the nRF5340, PMIC and conversion losses. However, each comparison was performed on the same board using the same supply path and with the debugger disconnected.

Releasing PD while retaining POWER_EN = 0 increases the system input power by approximately:

115–120 mW when powered through VBUS;

96–100 mW when powered through VBAT.

Activating the mono audio path produces a much smaller additional increase relative to the software power-down state.

Datasheet question
Table 5 of the ADAU1787 datasheet specifies the power-down current with DVDD externally supplied at 0.9 V. We could not find the equivalent current specification for operation with REG_EN = 1 and DVDD generated by the internal LDO.

The “DVDD LDO Regulator” section also states that the LDO requires the CM voltage and that, when REG_EN = 1, the PDpin must be held low to achieve the lowest possible power-down consumption.

Could you please clarify:

What are the expected AVDD, HPVDD, IOVDD and internal DVDD LDO currents when:

REG_EN = 1
PD = 1
POWER_EN = 0
CM_KEEP_ALIVE = 0
KEEP_SDSP = 0
KEEP_FDSP = 0
XTAL_EN = 0

Is an increase approaching 100 mW relative to hardware power-down expected when the internal DVDD LDO and the control interface remain operational?

Is CHIP_PWR = 0x14 correct for the lowest software power-down state with the internal LDO, or should CM_STARTUP_OVER have a different value while POWER_EN = 0?

Is there any supported configuration that keeps the I²C/SPI control interface operational while reducing the consumption of the internal LDO and CM circuitry?

Do you have equivalent current measurements from the ADAU1787 evaluation board configured to use the internal DVDD regulator, with J12 open and J24 in the ON position?

We would like to determine whether this consumption is expected from the internal DVDD LDO/CM architecture or whether it indicates an implementation problem in our hardware.

Thank you.

hardware

ADAU1787

processors and dsp

Processors and Microcontrollers

power consumption