ADAU1467 Sample rate converter problem

Hello Robin,

This is a good one! I am setup in the lab to test the ASRCs, for other reasons, so I will look into this today.

Dave T

Hello Robin,

Sorry this took a little while. I verified the problem then I had to figure out the solution. I am the support person for this part for consumer customers but I was not on the design team that built the product. I work closely with them so this was a learning experience for me as well. So much to know about these parts!!

We did improve the SPDIF features in the 146x parts over the 145x parts in that they will now go up to 192kHz. Well, to make this work the internal clock has to be faster to give the digital PLL the ability to lock to the faster rates. So to maintain backwards compatibility there is a register setting for this internal sub-system clock speed. By default it is set to the old setting of the system clock divided by 2. To run at 192kHz fs you must change it to System Clock undivided.

Here is where the register setting is located: On the SPDIF Tab you will see this:

Change the SPDIF RX MCLKSPEED to the SYSCLK setting. If you are using the SPDIF Transmitter then change that register as well.

This took care of the problem for me on the bench.

Let me know if this does not take care of it.

Thanks,

Dave T