ADAU1701 upsampling+DF

no, there is a single clock for the core.

Regards

Miguel

I know this, and in my example core run on 96kHz clock, but input FIFO is clocked by INPUT_BCLK.

Can somebody verify this algorithm?

Regards,

Nazar

One more thing, 48 and 96kHz input data is always synchronous to DSP core clock.

Regards,

Nazar

version with synchronous multiplexer - https://imgur.com/a/Bqr4J

I think it will work then. There is an application engineer that has done this successfully in a similar way as you describe. I'll ask him to comment.

Regards

Miguel

Thx Miguel, i will wait for his comment.

Regards,

Nazar

Hello Nazar,

Sorry for the delay. I wanted to take the time to go into the lab and actually obtain some measurements and to test it in practice rather than only in theory.

You actually do not need to create a zero-order hold, you can simply hold of the last value then filter it. The advantage of this is that it will happen automatically in hardware and you do not need to do it in SigmaStudio.

In hardware the input serial port is simply a shift register that shifts in the individual bits using the incoming bit clock. Then once the incoming LRCLK falls, it transfers the contents of the shift register to a memory location to hold the value while the next word starts shifting in.

So the core will then read the contents of this register at some point during the program that runs every sample period. Reading this memory location does not change it or reset it. It only gets reset when the new value has completed shifting in and the LRCLK falls.

So with the core running at 96kHz fs, it will read the value twice since it has not updated due to the fact that the serial port is being clocked at a 48kHz rate. So this will give you a staircase-like waveform where every sample is repeated twice. This produces a lot of harmonics and so filtering everything above the 48kHz Nyquist will filter out those harmonics and give you a clean signal that is now running at 96kHz.

So I set this up on the lab bench. I used am Nth-Order Double Precision Butterworth filter set to a 12th order low-pass with a 24kHz cutoff and 1dB ripple. This was only for this demonstration, there are probably other filters that are better for this application. I saw you were using an FIR filter and that is certainly a good option.

Here is my SigmaStudio program:

So for a baseline, everything set to 48kHz fs I sent in a signal from the Audio Precision serial transmitter through the DSP core then out the DAC to the Audio Precision analog input. The Audio Precision was set to measure THD+N with a very wide bandwidth of 22Hz to >500kHz to measure the out-of-band noise. The digital level was -1.0 dBFS.

Results was -69.4dBV of THD+N. With no filter.

So then I changed the core and the serial output port to run at 96kHz fs. I verified this by looking at the serial port LRCLK output.

With no filter I measured -43.1dBV of THD+N. Here is what the output looked like. This was a 1kHz sine wave.

You can see the stair-step in the waveform.

Then I enabled the filter in sigmaStudio and the new measurement was -69.37dBV THD+N with the filter with the core running at 96kHz and the serial data coming in at 48kHz. The waveform looked like this:

Now it looks normal again.

I do want to add for others that may read this in the future. This only works because the difference in the sample rate is exactly 1/2 the core rate. They are running on the same master clock so they will not drift. This is not really a sample rate converter for asynchronous signals nor for any rate. If the rate difference were 1/.4th then there would be four samples repeated and it would probably still sound OK. If it were 1/3rd the rate, then the sample memory location would be updated in the middle of a sample period every third sample. The memory can only be read by one thing at a time, so when the memory is being updated it would not be available to the core and you would get a zero or 0xFFFFFF. If the sampling rates were uncorrelated then you would get random clicks and pops and I think the serial port might not even work. That would have to be another experiment.

Good luck on your project. I hope it goes well!

Dave T

Dave, this is interesting! Somehow I remember accidently doing something like this in one of my experiments hooking two eval boards together via I2S -- and I was quite surprised to find it worked.

Hi Dave, thanks!

But if you use S/H(ZOH) instead of zero stuffing(RTZ) you need to compensate sin(x)/x HF droop caused by S/H(~3db on 20kHz with 48kHz SR), this can be done in following antialias FIR.

Regards,

Nazar