ADAU1701 I2S issue with connecting master signals
I am trying to do something I thought to be simple, but something strange happens.
In order to use ADAU1701 as a master:
- Bridged MP10 to MP4 and MP 11 to MP5, short wire on the print.
As soon as I create the connections the clock signals disappear from the scope. I have loaded a design to generate a simple 1000 hz sinus and the sound turns silent too, after I connect the second bridge. So, it seems the DSP halted. The DSP only comes back after a power cycle.
- Serial output is set to master mode, LRCLK, /256, delay by 1, 16 bit, /8.
- Serial output is I2S
I am using an elektor board like this on ADAU1701 Universal Audio DSP Board .
Rather complex analog I/O designs work great, it is just an USB input that causes trouble. For that I am experimenting with the mini streamer, in slave mode, by the way.
Any ideas what am I missing?
Jan-Willem
Audio Signal Processors
SigmaDSP Audio Processors
adau1701
Hello Jan-Willem,
Can you send your project?
It looks like you want to run at 192kHz fs?
From what you mentioned I think you meant to say that the framesync frequency is Internal clock / 256. This would give you 192kHzfs.
For !2S is a stereo format with 64 bits of data per frame. (Sample period) So you will need to have the bitclock run at 64x fs. which is 12.288MHz. You get this by setting the BCLK to be internal clock /4 not the divide by 8.
You also want to use all 24 bits. There is no reason not to do that. You do not have to use all the bits on whatever is receiving the data but it simplifies the setup and make the signal be a standard I2S format.
Now, the big question is what is going on with the master clock? The master clock MUST be correlated with the sampling rate clock, the LRCLK. So when running at 192kHz the master clock MUST be 192kHz x 256 = 49.152MHz.
There MUST be exactly 256 clock cycles in each frame and if there is not it will simply stop running.
So I am guessing that you are not using the master clock from the USB interface? If you have to switch master clocks while the part is running can be problematic. The PLL should really be shut down and then restarted so it can properly lock to the new master clock. Is there a controller in your system that could do this?
Usually for systems using USB I would recommend moving up to the ADAU1442 or the ADAU1452/51 because they have sample rate converters built in. Then they can adapt to any incoming sample rate and are not bound by having to be divided down from a master clock. But then you would need some codecs which complicates the design.
Another thing, are you checking the compiler output file to make sure you have not exceeded the 256 instructions when running at 192kHz fs?
Thanks,
Dave T
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