ADAU1467 LRCLK and BCLK master and slave settings
Thread Summary
The user asked about configuring BCLK and LRCLK for ADAU1467 in a system with 4 TDM8 streams on each input and output line. The final answer explains that the ADAU1467 must be set as the clock master for both input and output ports, with all other ports slaved to the master port. For TDM mode, separate master outputs are required for each TDM port. The LRCLK and BCLK can be re-purposed for other functions if needed.AI Generated Content
Hi,
I would appreciate clarification for B and LR clocks for the ADAU1467.
The system we have under design has 4 TDM8 streams input on each of the input lines, and 4 TDM8 streams outputs on each of the output lines. The MCLK signal is fed in from another source.
We want to set up the ADAU1467 as the master to output aligned LRCLCKs and BCLCKs to the other codecs in the system and to align all of the inputs and outputs of the ADAU1467.
Would the setting be corrects if we set up the serial ports in SigmaStudio, as follows:
Serial input Port 0 fields BCLK and LRCLK to master
Serial input ports 2,3, and 4 as slaves to CLK domain 0
All serial output ports including port as slaves to CLK domain 0
Thank you-Fred
Audio Signal Processors
adau1467
SigmaDSP Audio Processors
Fred,
Sorry for the delayed response. There is a slightly strange behavior with clock masters and slaves on the ADAU145x/6x parts. The master/slave relationships are separate for inputs and outputs. There is no way of directly slaving an input to an output clock, or vice versa. Therefore, in your example above, serial output port 0 would also need to be a clock master, and all other output ports would slave to output port 0. In other words, the output would look exactly the same as the input.
If you would like to have the ADAU1467 be the clock master at the core rate, the are a number of ways to do it depending on your hardware. The simplest method is to have one serial port (for example, input port 0) be the clock master, and connect all of the other ICs on your PCB to the same signal net. For the DSP itself, you can slave all of the other input ports to port 0 internally. As far as the outputs serial ports, you can either:
(a) connect the LRCLK net to one of the serial ports (for example, output port 0) and set output ports 1, 2, and 3 to slave to output port 0.
(b) set output port 0 LRCLK to be a master and leave the pin as a no-connect, and slave the other three output ports to port 0. This would have the same effect as above since both input and output LRCLK outputs would be slaved to the core rate.
In either case, note that you can re-purpose the six slave LRCLKs and MPx (GPIO) pins if you'd like since the functionality is multiplexed.
If the bit clocks are all running at the same rate (e.g. I2S/stereo), than you can use exactly the same configuration for BCLK. If you are using any of the ports in TDM mode, then they would, obviously, need to separate master outputs.
Ken
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