Max Inst (cycles) with Multirate project
Hello,
I have a question about a Multirate project running on ADAU1452 (see attached part).
Looking on Compiler Output, I have :
Compile succeeded : 0 errors, 0 warnings
Fs=192kHz - 67% (1029 cycles)
Fs=96kHz - 15% (904 cycles)
Fs=12kHz - 2% (405 cycles)
The sum gives 67+15+2=84%.
However, I discovered by measurements that dsp seems overloaded (incorrect frequency response).
Performing several tests, I discovered that dsp becomes overloaded at around 78% (addition of each percentage).
But some project seems OK at 78% and other not.
So I would like to know if there is a precise way to know the maximul available ressources in a Multirate project.
Best regards,
CyrilleD
Audio Signal Processors
adau1452
SigmaDSP Audio Processors
Hello Cyrille,
We are working on a runtime check for instruction cycle usage but it is not ready yet. The compiler output does have some hardware assumptions. So let's eliminate these possible causes.
What is the frequency of the MCLK coming into the DSP?
Is it from a crystal or a system clock?
How does the signal look on a scope? Is it low or does it have lots of reflections in the waveform?
You have the PLL set for a 24.576MHz MCLK input. If you happen to be running the MCLK at a lower frequency then you are reducing MIPS. Since you are running the serial port as a master you would be seeing the LRCLK at the wrong frequency if the incoming MCLK is low. So that is one way to test that the core is running at the correct rate.
I will ask the programmers to see why you are having these problems. Thanks so much for attaching your project, it is very helpful.
Dave T
Hello Dave,
Thanks for your answer and for asking programmers why I have these problems.
To answers your question, see my answer below in BOLD :
What is the frequency of the MCLK coming into the DSP? MCLK is at 24MHz.
Is it from a crystal or a system clock? It comes from a system clock.
How does the signal look on a scope? Is it low or does it have lots of reflections in the waveform? The signal has not a very wide amplitude, but it seems clean.
You have the PLL set for a 24.576MHz MCLK input. If you happen to be running the MCLK at a lower frequency then you are reducing MIPS. Since you are running the serial port as a master you would be seeing the LRCLK at the wrong frequency if the incoming MCLK is low. So that is one way to test that the core is running at the correct rate.
Configured sample rate on ports where we are master is 192kHz and the measured LRCK matches at 192kHz
Best Regards,
Cyrille
Hi Cyrille,
Did you ever get to the bottom of this?
I am seeing very similar behavior on a project I am working on. For me it seems like all streams only complete processing if the total number of cycles used at all rates combined fits within the budget of the fastest rate.
It would be great to hear if you had any success getting your multi-rate project to work.
I found out what was going on with my design. It turns out that the indirect parameter access table was using a bunch of cycles that were not being accounted for in the "Compiler Output"
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