Generating right BCLK Adau1450
Hi All,
I am using a Adau1450 with three I²S inputs and three I²S outputs. Output0 is master of BCLK and LRCLK and should generate a LRCLK of 93750Hz. For two channels, BCLK should be 93750*32*2 = 6Mhz
The DSP is clocked on MCLK with 24.0MHz. I attached an example file (lend from Dave Thib: "ADAU 1450 I2S and GPIO output issues ") what I changed a bit to set the proper outputs and enabling only CLCKGEN1. PLL devider is set to 8 (PLL input frequency=3.0Mhz), PLL FEEDBACK DIVIDER is set to 98 (PLL output is 98*3=294/2=147MHz). According to my calculations, I need to set M to 49, N to 32 in order to generate a BCLK of 6Mhz ( (147MHz/1024)*32/49)=93750. But all what I get is a BCLK of 9.18Mhz. I get around 6Mhz when I change M to 98
Does anyone see my flaw? What I also found is, that the BCLK only changes when M is about 3 times N. If that condition is not met, BCLK is 9.18MHz. When M is larger than (3*N), I can reduce BCLK to, for example, 6MHz...
Oh, I'm using SigmaSudio version 3.15, Build 2, Rev 1721
Hope someone can point me in the right direction :-)
With kind regards,
Reini
Audio Signal Processors
adau1450
SigmaDSP Audio Processors
Hi, I found the solution myself :-) It's not that difficult, because I used the 147Mhz pll output instead of the 294Mhz. Apparently, the core runs on 147Mhz, but the input for the clockgenerators is actually 294Mhz. Using that frequency, I calculate an M=294 and an N=96. These values give me a BCLK of 6MHz
Sorry to bother you all...
With kind regards,
Reini
Hello Reini,
You are really close to right with your understanding and it is a bit confusing.
The PLL output is in the 294MHz range for the 1452/51/50 processors. This way the PLL is running in the range it is best to run in.
What we do internally is to divide the PLL output by two but then we adjust the dividers going into the clock generators. Instead of them being 1024 they are 512. So the result is that the calculations you make for the 294MHz system clock also work fine for the 1450 with the 147MHz system clock. It all adjusts properly. Sorry for the confusion. This keeps the power consumption internally low by dividing down the PLL output.
So glad you got it figured out. It is an interesting sample rate you are running at.
Dave T
Hello Dave,
we use the 93750Hz samplerate to force an external (and optional) SRC to resample incoming signals. That's the only reason for the 93750Hz :-)
Thanks again for your explanation!
With kind regards,
Reini
Hello Reini,
That is brilliant! One of our designer once told me that the most difficult thing for an ASRC to do is to go between two almost identical sample rates! The coefficients become really small and can cause issues. So by guaranteeing the difference in the rate is a little more than 2% you will have the ASRC doing work with a more comfortable ratio.
Dave T
:-) exactly!
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