ADAU1452: Is a clock with 1% duty cycle allowed as input clock?

Hello takumi3952,

Can you give me the rest of the information about the configuration of clock Gen 3?

Generally, the min pulse width of a signal into the DSP is going to be 1 MCLK period but in this case 1% of 750 Hz is greater than 1 MCLK period I would guess. I actually do not know what the MCLK frequency is in your system. I assumed 12.288MHz.

I do not see any detail in the datasheet on the pulse width of this external input to the clock-gen 3.

I will ask one of the design engineers. I am still waiting on a response from your earlier question.

Dave T

Hi Dave,

Thanks for your reply.

The above is my clock_control setting. I use 1452MINIZ board.

External clock is inputted via LR_CLKIN3/MP13(J2-4) port.

In this case outputted clock stops sporadically.

If you need further information, please let me know.

Thanks and Regards,

Hello takumi3952,

I responded to your other post with some important details. Since these two posts have a similar topic I would like to point other readers to the other post.

https://ez.analog.com/message/327395-re-adau1452-clock-generator-3-input-restriction?commentID=327395&et=watches.email.thread#comment-327395

Dave T