AD1938 Configuration: ADC sample rate 44.1KHz, DAC dample rate 192KHz

Hello Ronan,

This is a quick reply.

The PLL only has one set of rates as an output. So that rate can be divided by the ADC and DAC. So in the DAC control and the ADC control registers you can set them to different rates but they are only multiples of the PLL rate.

So depending on your MCLK input, let's say it is 12.288MHz so that you will get 48kHz rate for the base rate. You could set the ADC to 48kHz and the DACs to 96kHz. A multiple. Or 192kHz.

Should you want to run at very different rates like 48Khz and 44.1kHz, then you have to set up the clocking differently.

You would have to run one half of the codec off of the PLL and have the PLL input be an LRCLK. You would have to have the correct loop filter components as well. Then you run the other half of the codec directly off of the MCLK input. The MCLK has to be 512 x fs.

If you do this then you should be aware of a bug I found a couple of years ago. If you use the PLL for the ADC and then directly clock the DACs. it works fine as long as the PLL is always locked and always has an input. Should the PLL lose its input and then lose lock, it will mute the DAC. So I guess this is a case for running the DAC off of the PLL and the ADC being directly clocked.

Just thought I would mention it.

Dave T