1701 MCLK requirements
in the ADAU1701.
Can the BCLK on an I2S be on a different phase than the MCLK?
The I2S is slave. The BCLK origin clock is internal to the I2S master.
1701 get's another clock source at MCLK.
Is it valid?
Audio Signal Processors
SigmaDSP Audio Processors
adau1701
Hello,
If the master is not locked to the same MCLK, or the source of the MCLK, then it is not valid. The two clocks will drift so that some times there will be too many or too few MCLK transitions during a frame. This will cause issues with the 1701.
The BCLK and master clock do not have to have their edges aligned but there must be the correct number of MCLK cycles per frame.
You can use a BCLK output of a serial port to drive the MCLK input pin. It must be all setup to the correct frequency but it can be done. Just keep in mind that the power up initialization only happens once the master clock it present so you must account for that and then the clock cannot go away.
Dave T
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