ADAU145x Clock Configuration of Serial Input Port

Tony,

Yes. This configuration will work as drawn. Only one master clock (MCLK) source is shown in your system, which is a requirement when using TDM16 inputs (i.e. without passing through the ASRCs). Although the ADAU145x is a shown as a bit clock and frame sync slave to Device A, it is driven with the same external MCLK as Device A so the direction of these signals is arbitrary. It doesn't matter which device divides the MCLK signal. Device B will be synchronous, as well, since it is a clock slave to the ADAU145x. Note that the MCLK for the DAC is not shown in this diagram. It should be driven with the same external MCLK.

Ken M

Hello TomY,

Let me add to what Ken has said.

You are correct in that even though the Device A and the ADAU1452 are running on the same master clock, the actual start of the LRCLK will be different. We have the internal resync to align the data to the internal core start of the frame but if you look at the actual LRCLK out of device A and the LRCLK being sent out to device B they will most likely be different. Since they are locked to the same master clock it will not change but each time the system turns on it will be a different delay. Fortunately, there is a way to solve this issue. The core start pulse can be sourced from the serial input ports. So simply set the start pulse register to come from serial port 0 and that will synchronize the core to the LRCLK start of device A. Then the internal clocks being sent to device be will be the same.

It is important that device A be stable and always outputting clocks otherwise the core will stop.

Regarding device B and having it sync to only BCLK and LRCLK: I would not recommend this be done while running at TDM16 rates. The timing margin for most devices to receive the BCLK edge and turn it around to output the next bit reduces the already tight timing of a TDM 16 signal. It will require good PCB layout techniques and good transmission line practices. I would suggest you run MCLK to device B. Then run the ADAU1452 serial port 1 with a combination of master and slave. Have the LRCLK be a master and the BCLK be a slave. This way both device A and B will be on the same LRCLK phase but the BCLK will be generated by device B so its data output timing will be aligned with the BCLK timing. This is provided device B can operate in this manner.

I concur with Ken in that when running at TDM 16 it is a good idea to have all the parts running off of the same Master Clock.

Dave T

The key requirements are (1) there be exactly one nominal sample rate at which the core is running corresponding to one master LRCLK, (2) the LRCLK of all of the inputs and outputs are aligned, and (3) the core start pulse is set to synchronize with (or be) the LRCLK master. In your diagram, Device A serves as the LRCLK master dictating the system sample rate. As Dave says, this can be achieved by slaving the core start pulse to Device A, and the making the SigmaDSP LRCLK master on all of the other serial ports.

Note that the bit clock and data do not need to be evenly spaced within an LRCLK sample frame. The serial sample data will be valid as long as every bit of every channel is transferred before the next sample begins. This is why Dave recommends that Device B be an LRCLK slave and BCLK master. At the high data rates of TDM16, it is safer to have Device B generate the bit clock that latches the data that it's sourcing because it provides more timing margin than it would have as bit clock slave.

Ken M

Hello, Ken and Dave

Thank you much for your answer.

Actually, I did not recognize that the DSP core can select to synch with which clock source by START_PULSE register.
So, it was good information and been very helpful.
And also, I understood that I need to be care for timming margin between ADAU145x and Device B.

I will proceed this system design based on your advice.

Again, thank you very much!!

Best regards, TomY

Hello TomY,

I apologize but I have to back up on this setup. I thought about it and then today I conducted some tests using evaluation boards. The Start Pulse register will synchronize the start of when the program runs during each sample period but it will not change the internal LRCLK edge. That will still be different from the incoming LRCLK. So setting port 1 to master will not give you an LRCLK that is lined up with the edge of the Device A LRCLK. Setting it to slave from serial input 0 will send the clock to the serial input port internally but it will not send it out of the pin.

So the only way to do this will be to distribute the LRCLK and BCLK signals to both serial input ports and to Device B. All external to the DSP. Since they are all on the same master clock the DSP will synchronize to it without the need of using ASRCs on the input. But we will not be able to output an LRCLK and BCLK that is exactly synchronized to the input from device A. The edges will always be a little off.

So make provisions for connecting these clocks externally.

Dave T

Hi, Dave

Thank you for your additional answer.

I will consider to change that BCLK/LRCLK of each Port connect from Device A externally.
ADAU145x is fully slave.
I think it is simple and safety.

TomY