ADAU1701 multipurpose pin configuration
Hi, community,
I tested very simple configuration of ADAU1701 - just one sine source routed to DAC0 output. I found out, that output signal disappears, as soon as MP5 (physical pin 9) configured as BCKI input in Sigma Studio. Should it be like that ? Thanks !
Audio Signal Processors
SigmaDSP Audio Processors
adau1701
Hello,
Not sure if it helps, but when I set the MP5 config on my ADAU1701MINIZ board to bclk_in, the sine wave source continued to sound. I had used DAC2 instead of DAC0; however this shouldn't matter as all the DACs are identical.
Thanks,
I found that everything is OK, if i remove input signal applied to Bclk_in.
So, if MP5 is set as Bclk_in, and signal on this input is present (from DIR9001), everything is bad. If input signal is not present, or pin configured not as input, everything is good.
However, it is obvious now, that ADAU1701 cannot work with external clocks, while being clock master. Question closed.
Hello Oskars,
The question is not closed.
I just went into the lab and loaded in a small program onto the ADAU1701 mini eval board. I set MP5 to BCLK_IN and took the BCLK output of the Audio Precision serial interface and applied it to the BCLK_IN pin and no change. The program works just fine.
The BCLK_IN pin is always a slave on this part. Only the serial output port can be a master or a slave. Normally, you would take the BCLK_OUT and route it to the BCLK_IN and also send it to an external device.
Then the other thing that perked my interest is that the BCLK in only used to clock the bits into the shift register. It does not interface at all with the clocking system in the part. The LRCLK is what needs to be synchronous to the master clock and to the core sample rate. The BCLK only has to be the correct number of transitions at the correct time to clock the data into the shift register so that at the end of the frame it will be transferred into the core.
So this means there is something else causing the symptom you see.
What is happening to the MCLK when the DIR9001 has a signal output? How are you dealing with master clock?
Dave T
Hi, Dave.
That is strange. In my case, any configuration of any other MP's make no changes in device behavior. I can configure MP4 as Lrck_in, apply signal to it (from DIR9001), nothing changes - i can generate, route and do other DSP things.
However, i see now, that it is impossible to use asynchronous digital inputs to ADAU1701 AND digital outputs clocked from MCLK in same time.
As i have two WM8804 S/PDIF outputs in my design (i do not use eval board), i have ADAU set as master to all i2s signal outputs and to MCLK as well.
If i apply external BCLK to MP5, configured as Bclk_in, there are things that happen:
All DAC's become disabled,
Any internal signal sources become disabled,
BCKO and LRCKO output remains.
Oskars
Hello Oskars,
Have you connected a scope to the MCLK to see what happens to it when you turn on the external BCLK? In this part you cannot run any asynchronous signals into the part. They must all be synchronized to the master clock. So you are right that it is impossible to use asynchronous signals in this part.
So the only thing that could kill the signals in the core is if the master clock went away or there is another clock fighting the MCLK signal, or if lots of noise enters into the system causing mis-triggers in the part. This is what I would look for. Also look at ground and power to see if there is a change there. There is a reason this is happening, it will just take some investigation to track down.
If you are using the PLL then another thing to look at is the PLL_LF pin. This will tell you if the PLL is locked or hunting for signal. If there is a lot of noise getting into this pin it can cause the PLL to lose lock.
See if these tests points us into a different direction.
Dave T
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