About SPI Slave Port of ADAU1452
Hello, ADI Support Team
I have a quick question about ADAU1452.
When SS (Slave Select) is High (Transaction is disable), is MISO Hi-Z?
Best Regards, TomY
Audio Signal Processors
adau1452
SigmaDSP Audio Processors
Hello, ADI Support Team
I have an additional explanation.
As the background of this question, I am considering to connect between MCU and ADAU1452 and other device via SPI.
And then, SPI master is MCU, and SPI slave is ADAU1452 and other device.
In this Multiple slave connection, when MCU is transmitting with other device, MISO pin of ADAU1452 should be Hi-Z, I think.
So, I'd like to confirm if MISO of ADAU1452 is Hi-Z or not, when CS is high (ADAU1452 is not selected).
Best regards, TomY
Hello, ADI Support Team
Regarding this question, I could find the following description in the datasheet.
Page 38 : SPI Slave Port
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The MISO signal remains three-state until a read operation is requested.
This allows other SPI-compatible peripherals to share the same MISO line.
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Therefore, I'm clear now.
If my point which I found is not correct, please let me know.
Best regards, TomY
Hello TomY,
Sorry for the delay. Yes, it will tri-state. It is designed to be in a multi-slave application.
Dave T
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