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ADAU1452 external SPI RAM "Write enable"

SigmaDSP & SigmaStudio Alex@@@123 Jan 8, 2017 00:00 3 replies Original on forum ↗
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Alex@@@123 Question
Jan 8, 2017 00:00

Hello all!

I'm trying to use the external SPI delay with Sigma Studio (3.14.1 beta). To extend the delay I'm using the Everspin 4Mbit MR20H40 MRAM - I ran in some issues and done a lot of investigations and I think I found the issue but don't know how to fix it. So here the problem in detail: The Everspin MRAM requires you to send a write enable (0x06) one time only after boot-up. After this it is using common read (0x03) and write (0x02) commands. Unfortunately when using the RAM with the ADAU1452 it didn't work - however looking at the scope output it is visible that the required (0x06) for write enable is not written correctly after boot up. As you can see in the picture it is sending a 0x01 followed by 0x40. (This looks like an access to the status bit register and a enable of a W/R flag but is not sufficient for the MRAM). The 2nd plot shows that after receiving all data from the self bootup EEPROM, this is the only command which is send before starting the continuous read/write sequence. Since the MRAM is non volatile the read command shows an output on the MISO line (green trace). Those values where previously stored in the MRAM using an arduino for debugging purpose - so it also shows that the ram is generally working and is accepting read commands but it is not accepting write commands since the write enable was not written correctly. (When you listen to the DSP output you can hear the looped audio data which was previously stored in the RAM with the arduino - so the delay block is reading the samples correctly but can't overwrite them since the ram doesn't accept the write commands)

For experimenting I modified the values in sigma studios external SPI delay block as followed: "Read Instruction" from 3 to 7, "Write Instruction" from 2 to 4 and "Write Enable" from 6 to 9 (see picture). The scope output shows that changing the values for "Read instruction" and "Write instruction" are applied correctly however changes to "Write Enable" don't change anything. To see if this problem is really causing the issue I used some arduino code to write the "Write Enable" 0x06 to the MRAM, kept it powered and then connected it to the ADAU1452 - and it worked. (I also tried a 1Mbit ram with the ADAU1452 and I think the only reason that it is working is because it doesn't need a special "Write Enable" command - I also confirmed that with some arduino code)

To investigate further I compared the compiler export output. It shows that all changes in the SPI block are correctly stored in the IC1.xml file (see: picture)

In addition the changes of "Write Instruction" and "Read Instruction" where reflected in the IC1.h file - however the change to the "Write Enable" value didn't do anything to the compiler output (see: picture).

So my guess is that somehow the compiler ignores changes of the "Write Enable" values and is using a hard-coded 0x01&0x40 instead. Or that the SPI MOSI should write the required 0x06 between "0x01&0x40" and the first "read/write" command but since the compiler doesn't save it correctly nothing is written.

So I'm wondering if I can change this somewhere and it is only a setup issue on my side or if it is a compiler problem?

Any help would be highly appreciated!

Thanks,

Alex

P.S. Just in case somebody is also looking to use a larger RAM for the external SPI delay. I also tried the Cypress 4Mbit FRAM CY15B104Q - this RAM will not work because it requires the write enable instruction every time before a write instruction is used.

Audio Signal Processors

adau1452

SigmaDSP Audio Processors

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Alex@@@123 Reply
Jan 11, 2017 00:00

Hi,

just in case somebody else runs into the issue and needs a solution. I came up with a hack which is not nice but working. I'm using a small Attiny controller wired to the DSP-eval board. The controller is connected in parallel to the MRAM to SCLK, MOSI and CS. As well as connected to the 3.3V regulated power of the board and the reset line of the DSP. After powering up the board it sets the board into reset (the 3.3V is still running and powering the system) and writes the "Write Enable" command to the MRAM. After that it releases the DSP reset. Before the DSP is released from reset it is important to re-define the attiny output pins (used for CLK, MOSI and CS) as input pins so that they don't interfere with the DSP SPI commands.

Alex@@@123 Reply
Jan 11, 2017 00:00

Unfortunately there is another issue I found with the external SPI described here: ADAU 1452 external SPI delay - but also here a "Solution" is possible. So overall the external SPI delay is running now with approximately 3 seconds delay.

Regards,

Alex

DaveThib Reply
Jan 12, 2017 00:00

Hello Alex,

I have reported this to the programming team.

Thanks for the great description.

Dave T