About ADAU1452's AC specification on Serial port.

"LRCLK setup to BCLK_INx input rising edge"

Could you tell me the exact definition of the rising edge please?

I also have the same question on tSIS as above.

Good question. I'm not sure but I'd presume that the DSP can perceive the rising edge anywhere in the transition region from VIL(max) to VIH(min), hence you would need to set up LRCLK 20ns before BCLK rises above 0.3*IOVDD and hold it for 5ns after it reaches 0.7*IOVDD, and similar for SDATA_IN except it only needs 5ns setup time.

About tSODS, the description says as below

"SDATA_OUTx delay in slave mode from BCLK_OUTx output ”falling edge”."

However, it seems that you measure it with the rising edge on figure 6.

That looks like an error in the figure to me, those markings make no sense for this measurement. I'd guess that figure 6 is based on a copy of figure 5 but it was insufficiently edited.

Also that description should of course say "from BCLK_OUTx input" since it's in slave mode. There's more confusion between IN/OUT in the pin name and whether that pin is an input (slave) or output (master), e.g. tLIS is described as being for BCLK_INx while it of course also applies to BCLK_OUTx in slave mode (or if it doesn't then those timings are missing).

About tSODS, when BCLK is 24.576MHz, the BCLK period is 40.7ns. And the half period is 20.35ns.

However, the max of tSODS is defined at 35ns.

This amount of delay doesn't surprise me, but you're right that it's going to be problematic at the highest bitrates.

So, I've tried to combine these observations and my interpretations thereof into a hopefully accurate timing diagram for slave mode (both inputs and outputs) at the highest bitrate, showing a frame sync and the surrounding two clock cycles:

(note I renamed LRCK to FS since the high bitrate implies it'll be multichannel TDM rather than I²S):

The output delay effectively causes a 180 degree phase shift. It may be possible to deal with this by configuring either the ADAU145x or the other end to use inverted BCLK polarity, but you'd need to check whether the resulting frame sync timing would be compatible. Note also that the output hold time specification is absent in the datasheet! I've just inserted a few nanoseconds here for illustration, but it could easily be significantly larger, which would make timing closure easier to achieve. Analog needs to clarify this.

At such high bitrates, I would suggest making the data output side also the master. When DATA, BCLK, and FS are all driven by the same chip and travel together to the recipient, the risk of timing problems should be minimized.

matthijs

Thank you so much for your comment!

About the tSODS AC spec, I've found a register bit that can solve all the mystery.

we can adjust "drive strength" depending on how fast BCLK is coming in.

If using 25MHz BCLK, the AC spec would be severe, so setting the drive strength as maximum, then the tSODS delay became just 5ns.

Thank you

Yuta M

Thanks Yuta,

I am trying to get caught up on EZ posts.

The datasheet specifications were developed with the drive strength set to the weakest setting. This is fine for lower BCLK rates but not for the higher rate. The correct setting will depend on the PCB layout and design of the transmission line. Going to the strongest will not necessarily be the correct setting for best signal integrity.

Dave T