Serial Port Clock Domains in ADAU1450
In ADAU1450, Do we require seperate clock domains (LRCLK and BCLK) for each Serial data input and output?
Audio Signal Processors
sigma300
serial port
adau1450
SigmaDSP Audio Processors
Hello Binu,
No you do not. If they are all coming from the same clock domain then you can simply run one set of clocks into one of the serial ports and have the other serial ports slave to that clock domain. If they are coming from different sources then you will have to run the clocks for each port. All of the sources will have to be running off of the same master clock.
There is one small bug that shows up if you are being the clock master. If you set one port, let's say port 0, as a master and send those clocks to another device. Then you are also sending serial data to the same device using port 1. So you select to slave from port 0. The result is that port 1 will have no LRCLK. The work-around is to just set port 1 also as a master since they are using the same clock anyway. You do not need to actually use the signals on the pins but this makes the internal connection for the shift registers. You can even still use the LRCLK as GPIO.
There is one other detail. If you are slaving from one device and you have serial input AND output ports going to and from the device. You will have to run the LRCLK and BCLK to one port on the input side and one port on the output side. There is no internal connection to slave an output port from an input port or the other way around.
Thanks,
Dave T
Hello Dave,
Thanks for the response.
Now I got it. We need individual LRCLK and BCLK only if the clocking domains are different else we can use any of the LRCLK_IN and BCLK_IN for SDATA_IN
Thanks
Binraj
Just found this post after several days of searching. Had been pulling my hair out over this...
Seeing the exact bug described on a board I designed. I am using port 0 as output, with LRCLK and BCLK both as master. I set port1 to slave from clk domain 0, and get no data out. If I select LRCLK to master it works.
Assume this bug is still present as was said 4 years ago?
Does this bug affect BCLK as well, i.e. should this also be set to master on port 1 to ensure it works properly? Or does the ADAU1452 not care about BCLK?
Thanks in advance.
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