SPDIF/SRC freezes on DC offset

I have discovered a setting in the configuration registers named "SPDIF set hot enable", I have enabled it and it seems to be having some useful effect.

Although the data sheet links this setting to the Auxiliary outputs, which I don't believe I am using, it does seem to stop the DC offset from getting through to my output on SDATA_OUT3.

Any explanations?

regards

PhilipJ

Hi Phillip,

Which chip are you using?

Thanks,

Tyler

Hi,

I am using the ADAU1442.

I did some more investigation after posting yesterday with the following results.

The setting I found, "SPDIF set hot enable" was a "red herring" it didn't really do anything.

What is happening is that when I remove the SPDIF input signal, the internal SPDIF receiver freezes on the last sample it received, what else could it do!. I know this because the chip has a useful feature to take the I2S signal decoded from the SPDIF and sent it out of one of the MP pins. Monitoring this with a 'scope shows the value that it freezes on and this corresponds to the DC offset coming out of my DAC.

I found another thread where somebody recommended having an external MPU monitor the SPDIF lock flag and turn a MUTE on/off with it. Luckily I have a PIC micro and I have implemented this idea, it seems to work quite well.

It would be a serious problem though for anyone doing a design without an external controller as there appears to be no path for the SPDIF lock bit to be accessed in the SigmaStudio design.

regards

PhilipJ

Did you tried to insert a DC-block filter?

Best regards,

Lasse

Hi,

thanks for the suggestion, I did try one but it didn't seem to do anything.

I was in a bit of a hurry to get a solution out for our customer so I put it aside and moved on.

I will try again when the pressure is off and see if I can work out what I did wrong with the DC-block filter.

Thanks

PhilipJ

The DC block filter will definitely work to remove the DC from the signal once the SPDIF signal goes away.

The only reason it may not work in your system is if you are using the SPDIF input signal as the start pulse for the DSP core. In other words, synchronizing the core to the SPDIF signal. Then when the SPDIF goes away the entire DSP "freezes" on the last value. This is why we actually removed the SPDIF input cell from the 1452 so you have to go through the ASRC and so the core will be running off of a different clock.

Dave T