Clock failure cause ADAU144x malfunction
Hello,
i've noted that interrupting the system clock to an ADAU1442 can cause, as written on the datasheet, an unpredictable behaviour.
Mostly i get the audio data outputs frozen, so bclk and lrck are still running, while data line remains stuck to zero or
some low value. In this case, everything else but this, seems to work normally.
In other cases everything gets messed up and, in addition to muted outputs, it seems that no other internal operations
are carried out.
Currently i'm using CRC bit to check for program integrity, but it seems not affected during this malfunction due to
system clock disturbance.
On the datasheet it is written that the DSP must be kept in reset state while changing clock, but i don't want to change the clock at all.
I'm just concerned that if any disturbance occurs on the clock, i could have the system down without knowing that.
Is there any way to catch this condition?
Thanks for any help.
Tom
Audio Signal Processors
adau1442
SigmaDSP Audio Processors
Hello Tom,
Well, there are several strategies you can use. One of them is to have a readback cell in the audio path and see if it is changing. If it ever settles on just one value then audio is not passing thru the core. You could setup a timer to produce a slow square wave and send that to a readback cell. This will take some system resources so the first method may be best.
So I am concerned that you are having disturbances on the clock. I do not see that in our evaluation boards or in customer applications. Can you take a screenshot of the clock input (MCLK) with a scope and post it? Then I would like to look at your schematic and PCB layout to see if we could clean up the clock if needed?
Thanks,
Dave T
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EZ Admin
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