ADAU1451WBCPZ DSP PLL Lock
Thread Summary
The user is experiencing PLL lock issues with the ADAU1451WBCPZ DSP when using a 24.576 MHz external clock for 16-channel TDM output. The final answer suggests changing C401 to 5.6 nF and connecting the junction of C401 and C400 directly to pin 15 (PVDD) without a ferrite bead. Additional advice mentions that signal integrity and power/ground noise could also be contributing factors.AI Generated Content
For our new design we’re using the ADAU1451WBCPZ DSP.
Unfortunately I ‘m experiencing PLL lock problem.
The PLL lock way form shown below:
We’re using external clock 24.576MHZ for the 16 channels output TDM.
PLL fitter connection showing below:
I tried to adjust R413 in a range from 0 to 10 KOhm with no results.
The only if I changed C400 from 15pF to 4700pF I got clean 2V lock level.
Do you have any idea what is wrong?
Thank you
Mark Naiditch
Hello Mark,
The PLL loop filter is not properly implemented. C401 needs to be 5.6nf not pf. They also should be a C0G/NP0 style of ceramic cap but I cannot tell that from your schematic. I am just mentioning that. The type of cap has more to do with being stable at all temperatures.
Then the junction of C401 and C400 need to be connected directly to pin 15 (PVDD). Do not use a ferrite bead/inductor. The ferrite bead is very bad in this location.
This should fix the issue but this also can be caused by excessive power and ground noise which is a byproduct of signal integrity issues. To look into those issues I would need to see more of your schematic and also have a look at your PCB layout.
Dave T
Thank you,
Of course 5.6nF
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