ADAU1452 SPI burst mode writing, wait time between successive word
Hi,
The ADAU1452 SPI burst mode writing, should we add wait time between successive word transfers ?
In the initialization sequence, when the host writes data via SPI in the burst mode, the ADAU1453 does not work normally.
If I set the SCLK frequency to 50KHz or less, it works normally.
On the other hand, when I wrote the program and register data from the PC on the Sigma Studio, I probed the SPI signals and observed the waveform.
Then there were small wait time ( the SCLK stopped a while ) between successive word transfer, I found.
It seems that we can transfer data without wait as the following Figure 36
I cannot find any specification about it in the data sheet.
But are there any limitations or specifications when we use the SPI burst writing ?
ADAU145x date sheet ( rev. C )
Page 14 SPI Interface—Slave
Page 39 Figure 36. SPI Slave Write Clocking (Burst Write Mode, N Bytes)
Audio Signal Processors
adau1452
SigmaDSP Audio Processors
Hello,
There is no wait time needed between bytes. The USBi interface is a bit different in that there is the USB interface that has software interface and then there is the software and hardware of the Cypress IC that is used to translate from USB to SPI so that is why you see the delay in that signal.
Since you said the interface works below 50kHz SCLK leads me to think that this is an issue of PCB layout and termination of the clock and data lines.
I would be glad to look at your schematic and PCB layout if you like. It can be done over a private message if you do not want to post them on the open forum.
Dave T
Thanks for your reply.
In the single address mode, the SPI interface works normally with about 3MHz SCLK.
So it seems that this is not PCB hardware issue ...
I had encountered the similar issue when I use the SPI burst transfer on other ADI's processor product.
When the frequency of the SCLK is slow, no wait time is needed.
But the frequency is fast, the transferring issue occurs.
Then I have found that the issue is caused by the wait time specification between successive word transfers.
Could the ADAU1452's SPI interface have similar limitations ?
The Blackfin and the SHARC processor have same specifications.
For example, we can find below.
ADSP-BF592 data sheet (Rev.B)
Page 32
Table 27. Serial Peripheral Interface (SPI) Port-Slave Timing
tSPITDS : Sequential Transfer Delay
http://www.analog.com/media/en/technical-documentation/data-sheets/ADSP-BF592.pdf
ADSP-BF59x Blackfin Processor Hardware Reference ( Revision 1.2, February 2013 )
Page 476
SPI Slave Select Input Signal (SPISS)
"The minimum time between successive word transfers (T4) is ..."
http://www.analog.com/media/en/dsp-documentation/processor-manuals/ADSP-BF59x_hwr_rev1.2.pdf
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